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BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
The BT868/869 is specifically designed for video systems requiring the generation of high-quality flicker-free composite and Y/C (S-video) signals from various YCrCb or RGB digital streams. The BT868/869 accepts any input format from 640 x 480 to 800 x 600 resolution. The BT868/869 uses Conexant's UltraScaleTM technology to provide the most advanced vertical and horizontal scaling necessary for the display of non-interlaced data on interlaced devices such as the TV. The UltraScaleTM technology converts the lines of input pixel data to the appropriate number of output lines for producing a full-screen, high-quality image. The BT868/869 performs 5-line vertical filtering, which includes poly phase interpolation scaling for overscan compensation and flicker filtering. Horizontal scaling for overscan compensation is achieved by altering the encoder clock frequency. This approach preserves all of the high frequency components of the input signals, which are essential for the highest quality display of text intensive images such as web pages on TVs. The amount of flicker filtering and overscan compensation is programmable. Worldwide video standards are supported, including NTSC-M (N. America, Taiwan, Japan), PAL-B,D,G,H,I (Europe, Asia), PAL-M (Brazil), PAL-N (Uruguay, Paraguay), and PAL-Nc (Argentina). BT868 and Bt869 are functionally identical, with the exception that Bt869 can output Macrovision Level 7.0 anticopy algorithm.
Distinguishing Features
* Digital RGB or YCrCb non-interlaced input to interlaced or non-interlaced analog TV output modes: YCrCb Modes: - 16-bit 4:2:2 multiplexed 8-bit - 24-bit 4:4:4 multiplexed 12-bit - 24-bit 4:4:4 non-multiplexed 24-bit RGB Modes: - 15/16 bit 5:6:5 RGB multiplexed 8-bit - 24-bit 8:8:8 RGB mulitplexed 12-bit - 24-bit 8:8:8 RGB non-multiplexed 24-bit Digital RGB non-interlaced input to analog RGB noninterlaced (VGA/SVGA) output modes: - 15/16 bit 5:6:5 RGB multiplexed 8-bit - 24-bit 8:8:8 RGB mulitplexed 12-bit - 24-bit 8:8:8 RGB non-multiplexed 24-bit Support for NTSC/PAL outputs in the following modes: - Interlaced and non-interlaced outputs - S-video output (simultaneous with composite NTSC or PAL outputs) - Component YUV analog output mode 5-line vertical filtering scaling for overscan compensation and flicker filtering CCIR601 compatible input mode Luma and chroma comb filtering 3 x 10-bit DACs 6 MHz Luma bandwidth Macrovision 7.0 copy protection 80-pin PQFP package 3.3 V operation with 5 V tolerant IOs 2-line serial programming interface Power-Down modes Master/slave video timing operation TV connected register flag Automatic configuration
*
*
Functional Block Diagram
*
P[23:0] Input DEMUX Color Space Conversion Flicker Filter/Scaler FIFO
HSYNC* VSYNC* BLANK* FIELD SIC SID ALTADDR RESET* SLEEP SLAVE PAL XTALIN
Timing Internal Reference Serial Interface Video Encoder DAC MUX
FSADJUST COMP VREF DACA
DACB
DACC VBIAS BIAS GEN CLKO CLKI
* * * * * * * * * * * *
XTAL OSC XTALOUT
PLL
Clock Generation
Applications
* * * * Desktop/Portable PCs with TV-Out Living-room PCs Internet PC/TVs Internet Appliances
Data Sheet
100123B September 2000
Ordering Information
Model Number BT868KRF Bt869KRF Package 80-pin PQFP 80-pin PQFP Ambient Temperature Range 0 C to +70 C 0 C to +70 C Reduced Features No Macrovision Feature --
(c) 2000, Conexant Systems, Inc.
All Rights Reserved. Information in this document is provided in connection with Conexant Systems, Inc. ("Conexant") products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at any time, without notice. Conexant makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Conexant's Terms and Conditions of Sale for such products, Conexant assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF CONEXANT PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. CONEXANT FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. CONEXANT SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Conexant products are not intended for use in medical, lifesaving or life sustaining applications. Conexant customers using or selling Conexant products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale. The following are trademarks of Conexant Systems, Inc.: ConexantTM, the Conexant C symbol, and "What's Next in Communications Technologies"TM. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. For additional disclaimer information, please consult Conexant's Legal Information posted at www.conexant.com, which is incorporated by reference. Reader Response: Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and suggestions to tech.pubs@conexant.com. For technical questions, contact your local Conexant sales office or field applications engineer.
100123B
Conexant
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 1.2 1.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 GUI Controller Programmability and Frequency Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.3.8 1.3.9 1.3.10 1.3.11 1.3.12 1.3.13 1.3.14 1.3.15 1.3.16 1.3.17 1.3.18 1.3.19 1.3.20 1.3.21 1.3.22 1.3.23 1.3.24 1.3.25 1.3.26 1.3.27 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Auto Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Clocking and Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Master and Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Pixel Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 YCrCb Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 RGB Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Video Amplitude Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Input Pixel Horizontal Sync. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Input Pixel Vertical Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 Input Pixel Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 Overscan Compensation and Flicker Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 VGA Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Analog Horizontal Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Analog Vertical Sync. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Analog Video Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Video Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Subcarrier Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 Burst Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Chrominance Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Digital Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Subcarrier Phasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
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Table of Contents
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
1.3.28 1.3.29 1.3.30 1.3.31 1.3.32 1.3.33 1.3.34 1.3.35 1.3.36
Noninterlaced Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 Closed Captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 Internal Color Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 Macrovision Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 Output Connection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 Output Filtering and SINX/X Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34
2.0
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 2.2 2.3 Essential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Writing Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Reading Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3.0
PC Board Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 3.2 3.3 Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Power and Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 3.5.3 3.6 3.7 Device Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Power Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 COMP Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 VREF Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 VBIAS Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Electrostatic Discharge and Latchup Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Clock and Subcarrier Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Filtering Radio Frequency Modulator Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
BT868/Bt869 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.7.1 Data Transfer on the Serial Interface Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
4.0
Parametric Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 4.2 4.3 DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Appendix A. Scaling and I/O Timing Register Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Appendix B. Approved Crystal Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
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100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
List of Figures
List of Figures
Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 1-6. Figure 1-7. Figure 1-8. Figure 1-9. Figure 1-10. Figure 1-11. Figure 1-12. Figure 1-13. Figure 1-14. Figure 1-15. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 4-1. Figure 4-2. Figure 4-3. Figure A-1. Figure A-2. Figure A-3. Figure A-4. Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Flicker Filter Control Diagram--External Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Encoder Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Decimation Filter at Fs=27 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Interlaced 525-Line (NTSC) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 Interlaced 525-Line (PAL-M) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 Interlaced 625-Line (PAL-B, D, G, H, I, Nc) Video Timing (Fields 1-4) . . . . . . . . . . . . . . . 1-24 Interlaced 625-Line (PAL-B, D, G, H, I, Nc) Video Timing (Fields 5-8) . . . . . . . . . . . . . . . 1-25 Interlaced 625-Line (PAL-N) Video Timing (Fields 1-4) . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 Interlaced 625-Line (PAL-N) Video Timing (Fields 5-8) . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 Noninterlaced 262-Line (NTSC) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Noninterlaced 262-Line (PAL-M) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Noninterlaced 312-Line (PAL-B, D, G, H, I, N, Nc) Video Timing . . . . . . . . . . . . . . . . . . . 1-29 Three-Stage Chroma Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Luminance Upsampling Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 Power Plane Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Connection Diagram for Output Filters and Other Key Passive Components . . . . . . . . . . . . 3-3 Complete BT868/Bt869 Recommended Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 BT868/Bt869 Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 SID/SIC Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Master Mode with Flicker Filter Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Slave Mode with Flicker Filter Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Overscan Compensation, 640x480 NTSC, 20 Clock Hblank . . . . . . . . . . . . . . . . . . . . . . . . A-2 Overscan Compensation, 640x480 PAL, 20 Clock Hblank . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Overscan Compensation, 800x600 NTSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 Overscan Compensation, 800x600 PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
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List of Figures
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
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Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
List of Tables
List of Tables
Table 1-1. Table 1-2. Table 1-3. Table 1-4. Table 1-5. Table 1-6. Table 1-7. Table 1-8. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 3-1. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table A-1. Table A-2. Table A-3. Table A-4. Table A-5. Table A-6. Table A-7. Table A-8. Table A-9. Table A-10. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Data Pin Assignments for Multiplexed Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Data Pin Assignments for Non-multiplexed Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Programmability and Frequency Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Auto-Configuration Modes 0-3--RGB Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Auto-Configuration Modes 4-7--YCrCb Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Video Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Video Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Read-Back Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Data Details Defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Programming Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Typical Parts List for Key Passive Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Video Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Constant Values Dependent on Encoding Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Overscan Values, 640x480 NTSC, 1 Pixel Resolution, 2.5 ms Hblank . . . . . . . . . . . . . . . . . A-5 Overscan Values, 640x480 NTSC, 8 Pixel Resolution, 2.5 ms Hblank . . . . . . . . . . . . . . . . . A-7 Overscan Values, 640x480 NTSC, 9 Pixel Resolution, 2.5 ms Hblank . . . . . . . . . . . . . . . . . A-8 Overscan Values, 640x480 PAL, 1 Pixel Resolution, 2.5 ms Hblank. . . . . . . . . . . . . . . . . . . A-8 Overscan Values, 640x480 PAL, 8 Pixel Resolution, 2.5 ms Hblank. . . . . . . . . . . . . . . . . . A-11 Overscan Values, 640x480 PAL, 9 Pixel Resolution, 2.5 ms Hblank. . . . . . . . . . . . . . . . . . A-12 Overscan Values, 800x600 NTSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13 Overscan Values, 800x600, PAL, > 2.5 ms Hblank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
100123B
Conexant
ix
List of Tables
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
x
Conexant
100123B
1
1.0 Functional Description
1.1 Pin Descriptions
The pinout diagram is shown in Figure 1-1. Pin names, input/output assignments, numbers and descriptions are listed in Tables 1-2 and 1-3.
Figure 1-1. Pinout Diagram
VSS VSS_SI VSS_SO SID SIC VDD_SO VDD_SI ALTADDR VDDMAX PAL SLAVE SLEEP RESET* CLKI VSS_CO CLKO VDD_CO AGND_PLL VAA_PLL VDD
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD_X XTALOUT XTALIN VSS_X N/C N/C N/C DACA VAA_DACA DACB VAA_DACB DACC VAA_DACC AGND_DAC COMP VREF VBIAS FSADJUST AGND VAA
80-pin PQFP
VDD TEST BLANK* FIELD VSYNC* HSYNC* P[23] P[22] P[21] VSS_O VDD_O P[20] P[19] P[18] P[17] P[16] P[15] P[14] VSS_I VSS
100123B
Conexant
AGND NC NC VSS P[0] P[1] P[2] P[3] P[4] P[5] P[6] P[7] P[8] P[9] P[10] P[11] P[12] P[13] VDD_I VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1-1
1.0 Functional Description
1.1 Pin Descriptions
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Table 1-1. Pin Assignments (1 of 3) Pin Name
XTALIN XTALOUT VDD_X VSS_X VAA_PLL AGND_PLL CLKO VDD_CO VSS_CO CLKI
I/O
I O -- -- -- -- O -- -- I 63 62 61 64 59 58 56 57 55 54
Pin #
Description
A crystal can be connected to these pins. The pixel clock output (CLKO) is derived from these pins with a PLL. XTALIN can be driven as a CMOS input pin. Crystal oscillator supply pin. This pin should be tied to the digital supply. Crystal oscillator ground pin. This pin should be tied to the digital ground plane. Analog power for PLL. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. Analog ground for PLL. All AGND and VSS pins must be connected together on the same PCB plane to prevent latchup. Pixel clock output (TTL compatible). This pin is three-state if the CLKI pin provides the encoder clock. Clock output supply pin. This pin should be tied to the digital supply. Clock output ground pin. This pin should be tied to the digital ground plane. Pixel clock input (TTL compatible). This may be used as either the encoder clock or a delayed version of the CLKO pin synchronized with the pixel data input. Reset control input (TTL compatible). A logical 0 resets and disables video timing (horizontal, vertical, subcarrier counters to the start of VSYNC of first field) and resets the serial interface registers). RESET* must be a logical 1 for normal operation. Power-down control input (TTL compatible). A logical 1 configures the device for power-down mode. A logical 0 configures the device for normal operation. Slave/master mode select input (TTL compatible). A logical 1 configures the device for slave video timing operation. A logical 0 configures the device for master video timing operation. PAL/NTSC mode select input (TTL compatible). A logical 1 configures the device for PAL video format and Mode 1. A logical 0 configures the device for NTSC video format and Mode 0. Input threshold adjustment. This pin should be tied to VDD for 3.3 V input swings and GND for 5 V input swings. This pin does not affect the serial interface pins (SID and SIC). Alternate slave address input (TTL compatible). A logical 0 configures the device to respond to a serial programming address of 0x88; a logical 1 configures the device to respond to a serial programming address of 0x8A.(1) Serial interface clock input (TTL compatible). The maximum clock rate is 400 kHz. Serial interface data input/output (TTL compatible). Data is written to and read from the device via this serial bus. Serial interface input supply pin. This pin should be tied to the proper supply voltage for the desired serial interface operating voltage (i.e., tie to 5 V for 5 V serial interface compatibility).
RESET*
I
53
SLEEP
I
52
SLAVE
I
51
PAL
I
50
VDDMAX
I
49
ALTADDR
I
48
SIC SID VDD_SI
I I/O --
45 44 47
1-2
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table 1-1. Pin Assignments (2 of 3) Pin Name
VSS_SI VDD_SO
1.0 Functional Description
1.1 Pin Descriptions
I/O
-- -- 42 46
Pin #
Description
Serial interface input ground pin. This pin should be tied to the digital ground plane. Serial interface output supply pin. This pin should be tied to the proper supply voltage for the desired serial interface operating voltage (i.e., tie to 5 V for 5 V serial interface compatibility). Serial interface output ground pin. This pin should be tied to the digital ground plane. Test pin. Should be tied to VSS. Composite blanking control (TTL compatible). This can be generated by the encoder or supplied from the graphics controller. If internal blanking is used, this pin can be used to indicate the controller character clock edge. Field control output (TTL compatible) (Master Mode only three-state in slave mode). FIELD transitions after the rising edge of CLK, two clock cycles following falling HSYNC*. It is a logical 0 during odd fields and is a logical 1 during even fields. Vertical sync input/output (TTL compatible). As an output (master mode operation), VSYNC* is output following the rising edge of CLK. As an input (slave mode operation), VSYNC* is registered on the rising edge of CLK. Horizontal sync input/output (TTL compatible). As an output (master mode operation), HSYNC* is output following the rising edge of CLK. As an input (slave mode operation), HSYNC* is registered on the rising edge of CLK. Pixel inputs. See Table 1-2, "Data Pin Assignments for Multiplexed Modes," on page 1.05. The input data is sampled on both the rising and falling edge of CLK for multiplexed modes, and on the rising edge of clock in non-multiplexed modes. A higher bit index corresponds to a greater bit significance. Digital power for core logic. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. Digital power for digital inputs. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. This pin should be tied to the 5 V supply for 5 V tolerant inputs, Digital power for digital outputs. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. Digital ground for core logic. All AGND and VSS pins must be connected together on the same PCB plane to prevent latchup. Digital ground for inputs. All AGND and VSS pins must be connected together on the same PCB plane to prevent latchup. Digital ground for outputs. All AGND and VSS pins must be connected together on the same PCB plane to prevent latchup. Analog power. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. Analog ground. All AGND and VSS pins must be connected together on the same PCB plane to prevent latchup.
VSS_SO TEST BLANK*
-- I I/O
43 39 38
FIELD
O
37
VSYNC*
I/O
36
HSYNC*
I/O
35
P[23:0]
I
32-34, 23-29, 5-18
VDD VDD_I
-- --
20,40,60 19
VDD_O VSS VSS_I VSS_O VAA AGND
-- -- -- -- -- --
30 4, 21, 41 22 31 80 1, 79
100123B
Conexant
1-3
1.0 Functional Description
1.1 Pin Descriptions
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Table 1-1. Pin Assignments (3 of 3) Pin Name
FSADJUST VBIAS
I/O
I O 78 77
Pin #
Description
Full-scale adjust control pin. A resistor (RSET) connected between this pin and GND controls the full-scale output current on the analog outputs. DAC bias voltage. A 0.1 F ceramic capacitor must be used to bypass this pin to GND. The capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Voltage reference pin. A 0.1 F ceramic capacitor must be used to decouple this pin to GND. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Compensation pin. A 0.1 F ceramic capacitor must be used to bypass this pin to VAA. The capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Common DAC Analog ground return. All AGND and VSS pins must be connected together on the same PCB plane to prevent latchup. DACC Analog power. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. DACC output. DACB Analog power. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. DACB output. DACA Analog power. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. DACA output. No connect pins
VREF
O
76
COMP
O
75
AGND_DAC VAA_DACC DACC VAA_DACB DACB VAA_DACA DACA N/C
NOTE(S):
(1)
-- -- O -- O -- O --
74 73 72 71 70 69 68 65, 66, 67
Any unused inputs should not be left floating.
1-4
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table 1-2. Data Pin Assignments for Multiplexed Modes Rising Edge of CLKI Pin 24-bit RGB Mode
G4 G3 G2 B7 B6 B5 B4 B3 G0 B2 B1 B0
1.0 Functional Description
1.1 Pin Descriptions
Falling Edge of CLKI 24-bit YCrCb Mode
Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 Cb7 Cb6 Cb5 Cb4
15/16-bit RGB Mode
G2 G1 G0 B4 B3 B2 B1 B0 -- -- -- --
16-bit YCrCb Mode
Cr/Cb7 Cr/Cb6 Cr/Cb5 Cr/Cb4 Cr/Cb3 Cr/Cb2 Cr/Cb1 Cr/Cb0 -- -- -- --
24-bit RGB Mode
R7 R6 R5 R4 R3 G7 G6 G5 R2 R1 R0 G1
15/16-bit RGB Mode
R4 R3 R2 R1 R0 G5(1) G4 G3 -- -- -- --
16-bit YCrCb Mode
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 -- -- -- --
24-bit YCrCb Mode
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb3 Cb2 Cb1 Cb0
P[11] P[10] P[9] P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0]
NOTE(S):
(1)
G5 is ignored in 15-bit RGB mode.
Table 1-3. Data Pin Assignments for Non-multiplexed Modes Pin
P[23:16] P[15:8] P[7:0]
24-bit RGB Mode
B[7:0] G[7:0] R[7:0]
24-bit YCrCb Mode
Cb[7:0] Cr[7:0] CY[7:0]
100123B
Conexant
1-5
1.0 Functional Description
1.2 GUI Controller Programmability and Frequency Requirement Flicker-Free Video Encoder with Ultrascale
BT868/Bt869
TM
Technology
1.2 GUI Controller Programmability and Frequency Requirement
Programmability and frequency requirements for the GUI Controller are defined in Table 1-4.
Table 1-4. Programmability and Frequency Requirement Maximum Total Mode Pixels
640 x 480 800 x 600 1075 1075
Lines
665 835
Maximum Vsync to Active
117 147
Maximum Frequencies Line (kHz)
39.860 49.451
Pixel (MHz)
31.563 40.000
1-6
Conexant
100123B
100123B
Color Space Converter
BT868/Bt869
Input
Flicker Filter/Scaler
FIFO
IN_MODE[2:0] 000 = 5 Line 00 = Bypass 001 = 15/16 Gain 010 = 7/8 Gain 011 = 3/4 Gain 100 = 1/2 Gain 101 = 1/4 Gain 110 = 1/8 Gain 111 = 0.0 Gain 01 = Luma, Horizontal LPF1 10 = Luma, Horizontal LPF2 11 = Luma, Horizontal LPF3 001 = 2 Line 010 = 3 Line 011 = 4 Line 100 = Alt. 5 Line 1 101 = Alt. 5 Line 2 110 = Alt. 5 Line 3 111 = Alt. 5 Line 4 F_SELC[2:0] 000 = 5 Line 001 = 2 Line 010 = 3 Line 011 = 4 Line 100 = Alt. 5 Line 1 101 = Alt. 5 Line 2 110 = Alt. 5 Line 3 111 = Alt. 5 Line 4 00 = Bypass 01 = Chroma, Horizontal LPF1 10 = Chroma, Horizontal LPF2 11 = Chroma, Horizontal LPF3 000 = 1.0 Gain 001 = 15/16 Gain 010 = 7/8 Gain 011 = 3/4 Gain 100 = 1/2 Gain 101 = 1/4 Gain 110 = 1/8 Gain 111 = 0.0 Gain CLPF[1:0] CATTENUATE[2:0] 0 = Enable Chroma Psuedo Gamma Removal 0 = Enable Chroma Anti-Psuedo Gamma Removal DIS_GMSHC DIS_GMUSHC 000 = 1.0 Gain
F_SELY[2:0]
DIS_GMSHY DIS_GMUSHY DIS_YFLPF
YLPF[1:0]
YATTENUATE[2:0]
YCORING[2:0] 000 = Bypass 001 = 1/128 of Range 010 = 1/64 of Range 011 = 1/32 of Range 100 = 1/16 of Range 101 = 1/8 of Range 110 = 1/4 of Range 111 = Reserved CCORING[2:0] 000 = Bypass 001 = +/-1/256 of Range 010 = +/- 1/128 of Range 011 = +/- 1/64 of Range 100 = +/- 1/32 of Range 101 = +/- 1/16 of Range 110 = +/- 1/8 of Range 111 = Reserved
000 = 24-bit RGB Mux
001 = 16-bit RGB Mux
0 = Enable Luma Psuedo Gamma Removal
0 = Enable Luma Anti-Pseudo Gamma Removal
0 = Enable Initial Luma Horizontal Low Pass Filter
010 = 15-bit RGB Mux
Figure 1-2. Flicker Filter Control Diagram--External Use
011 = 24-bit RGB Non-Mux
Flicker-Free Video Encoder with UltrascaleTM Technology 1.2 GUI Controller Programmability and Frequency Requirement
Figure 1-2 illustrates the concept of flicker filter control.
Conexant
100 = 24-bit YCrCb Mux
101 = 16-bit YCrCb Mux
110 = Reserved
111 = 24-bit YCrCb Non-Mux
1.0 Functional Description
1-7
1-8
Video Timing Control, FIELD SYNC_AMP FSADJUST
1.0 Functional Description
RESET*
SID Registers
MY Sync Processor Internal Voltage Reference Y 10
Figure 1-3. Encoder Core
COMP
Y[9:0] + Closed Captioning, Macrovision + Luma Delay CVBS 10 2X Upsample
1.2 GUI Controller Programmability and Frequency Requirement Flicker-Free Video Encoder with Ultrascale
Figure 1-3 illustrates the BT868/869 functional block diagram.
Conexant
X + X 9 LPF 2X Upsample 9 4:2:2 to 4:4:4 Conversion C 10 Modulator and Mixer U/V 10 RGB 24
VBIAS
MCR
10 Out Mode 10 Out Mux
DAC
DACA
MCB
CRCB[9:0]
DAC 10 DAC
DACB DACC
Burst Processor
BST_AMP
TM
BT868/Bt869
Technology
100123B
RGB
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
1.0 Functional Description
1.3 Circuit Description
1.3 Circuit Description
1.3.1 Overview
The BT868/869 is a video encoder designed for TV output of non-interlaced graphics data, such as that found in a PC or some set-top boxes. It incorporates advanced filtering technology for flicker removal and overscan compensation which allows high-quality display of non-interlaced images on an interlaced TV display. The BT868/869 accomplishes this by minimizing the flicker and providing control of the amount of overscan so that the entire image is viewable. The BT868/869 consists of a Color Space Converter/Flicker Filter engine followed by a digital video encoder. The Color Space Converter/Flicker Filter contains the following: * * * A timing converter Various horizontal video processing functions Flicker filter and vertical scaler for overscan compensation
The output of this engine is fed into a FIFO for synchronization with the digital video encoder.
1.3.2 Reset
If the RESET* pin is held low for a minimum of two clock cycles, a timing reset and a software reset is performed. During a timing reset, the serial interface is held in the reset condition, the subcarrier phase is set to zero, and the horizontal and vertical counters are held to the beginning of VSYNC of Field 1 (both counters equal to zero). Counting resumes the next clock after rising RESET*. The serial interface registers are reset to zero. A software reset, which can be generated by setting the SRESET register bit, initializes all the serial interface registers to zero (except for PLL_INT, which is initialized to 0x0C). As a result, all output pins are three-state. The first 32 registers are then initialized to auto-configuration mode 0 (see the Auto Configuration section). The EN_OUT bit must be set to enable the outputs. The software reset can also be generated by setting the SRESET register bit. A power-on reset is generated on power-up. The power-on reset generates both a timing and a software reset. The power-on reset is generated by a time delay circuit triggered after the supply voltage reaches a value sufficiently high enough for the circuit to operate. As such, the device may not initialize to the default state unless the power supply ramp rate is sufficiently fast enough. Therefore, a hardware reset is recommended if the default state is required.
1.3.3 Timing Registers
After writing any registers, a timing reset is recommended by setting the T-bit.
100123B
Conexant
1-9
1.0 Functional Description
1.3 Circuit Description
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
1.3.4 Device Initialization
After a reset condition, the device must be programmed through the serial interface to activate video or output one of the other video standards and to enable the CLK0, HSYNC*, VSYNC*, and FIELD outputs.
1.3.5 Auto Configuration
The device can configure itself for one of eight combinations of video formats and input modes with a single register write. Tables 1-5 and 1-6 detail the eight available auto configuration modes. This feature reduces the software support required, yet allows full flexibility in generating video formats and timing. Once the device is configured, all the registers are accessible to modify the modes. For less common modes, the device can be configured for the closest mode, and only those registers that differ need to be programmed. To auto-configure the device, set the configuration bits (CONFIG[2:0]) to the desired mode. The device will initialize the first 32 registers (registers 0x3B to 0x5A), setting the BUSY flag in the process. When complete, the BUSY flag is cleared. The serial interface is not available when the BUSY flag is high except for monitoring the status register. If the mux mode is enabled, pins P[23:21] can also be used to externally configure the device to any one of the eight configuration modes. These pins directly emulate the CONFIG[2:0] register. In order to configure the device in this way, the EN_PINCFG register must be set. The desired state must be present on the P[23:21] pins for at least two clock cycles.
1-10
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table 1-5. Auto-Configuration Modes 0-3--RGB Input (1 of 2) Mode 0 NTSC 640x480(1) CLKO=28.195793 MHz DEC
H_CLKO [11:0] H_ACTIVE [9:0] HSYNC_WIDTH [7:0] HBURST_BEGIN [7:0] HBURST_END [7:0] H_BLANKO [10:0] V_BLANKO [9:0] V_ACTIVEO [8:0] H_FRACT [7:0] H_CLKI [10:0] H_BLANKI [8:0] V_BLANK_DLY V_LINESI [9:0] V_BLANKI [7:0] V_ACTIVEI [9:0] CLPF [1:0] YLPF [1:0] V_SCALE [13:0] PLL_FRACT [15:0] EN_XCLK BY_PLL PLL_INT [5:0] EN_SCART ECLIP PAL DIS_SCRESET VSYNC_DUR 625LINE SETUP 1792 640 132 150 96 381 34 212 0 784 126 0 600 75 480 0 3 5266 34830 0 0 12 0 0 0 0 1 0 1
1.0 Functional Description
1.3 Circuit Description
Register Name
Mode 1 PAL 640x480 CLKO=29.500008 MHz DEC
1888 640 138 166 104 449 46 242 0 944 266 0 625 90 480 0 3 4096 7282 0 0 13 0 0 1 0 0 1 0
Mode 2 NTSC 800x600 CLKO=38.769241 MHz DEC
2464 800 182 206 180 597 32 216 0 880 66 0 735 86 600 0 3 7373 15124 0 0 17 0 0 0 0 1 0 1
Mode 3 PAL 800x600 CLKO=36.000000 MHz DEC
2304 800 170 202 154 525 41 252 0 960 140 0 750 95 600 0 3 5734 0 0 0 16 0 0 1 0 0 1 0
HEX
700 280 84 96 60 17D 22 D4 0 310 7E 0 258 4B 1E0 0 3 1492 880E 0 0 C 0 0 0 0 1 0 1
HEX
760 280 8A A6 68 1C1 2E F2 0 3B0 10A 0 271 5A 1E0 0 3 1000 1C72 0 0 D 0 0 1 0 0 1 0
HEX
9A0 320 B6 CE 84 255 20 D8 0 370 42 0 2DF 56 258 0 3 1CCD 3B14 0 0 11 0 0 0 0 1 0 1
HEX
900 320 AA CA 9A 20D 29 FC 0 3C0 8C 0 2EE 5F 258 0 3 1666 0 0 0 10 0 0 1 0 0 1 0
100123B
Conexant
1-11
1.0 Functional Description
1.3 Circuit Description
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Table 1-5. Auto-Configuration Modes 0-3--RGB Input (2 of 2) Mode 0 NTSC 640x480(1) CLKO=28.195793 MHz DEC
NI_OUT SYNC_AMP [7:0] BST_AMP [7:0] MCR [7:0] MCB [7:0] MY [7:0] MSC [31:0]
NOTE(S):
(1)
Register Name
Mode 1 PAL 640x480 CLKO=29.500008 MHz DEC
0 240 88 129 73 140 645499916
Mode 2 NTSC 800x600 CLKO=38.769241 MHz DEC
0 229 116 119 67 133 396552378
Mode 3 PAL 800x600 CLKO=36.000000 MHz DEC
0 240 87 128 72 140 528951320
HEX
0 E5 76 79 44 85 20800000
HEX
0 F0 58 81 49 8C 26798C0C
HEX
0 E5 74 77 43 85 17A2E8BA
HEX
0 F0 57 80 48 8C 1F872818
0 229 118 121 68 133 545259520
Assumes 13.5 MHz CLK-D frequency.
Table 1-6. Auto-Configuration Modes 4-7--YCrCb Input (1 of 2) Mode 4 Mode 5 NTSC 640x480 PAL 640x480 CLKO=28.195793 MHz CLKO=29.500008 MHz DEC
H_CLKO [11:0] H_ACTIVE [9:0] HSYNC_WIDTH [7:0] HBURST_BEGIN [7:0] HBURST_END [7:0] H_BLANKO [10:0] V_BLANKO [9:0] V_ACTIVEO [8:0] H_FRACT [7:0] H_CLKI [10:0] H_BLANKI [8:0] V_BLANK_DLY V_LINESI [9:0] V_BLANKI [7:0] V_ACTIVEI [9:0] CLPF [1:0] 1792 640 132 150 96 381 34 212 0 784 126 0 600 75 480 0
Register Name
Mode 6 NTSC 800x600 CLKO=38.769241 MHz DEC
2464 800 182 206 180 597 32 216 0 880 66 0 735 86 600 0
Mode 7 PAL 800x600 CLKO=36.000000 MHz DEC
2304 800 170 202 154 525 41 252 0 960 140 0 750 95 600 0
HEX
700 280 84 96 60 17D 22 D4 0 310 7E 0 258 4B 1E0 0
DEC
1888 640 138 166 103 449 46 242 0 944 266 0 625 90 480 0
HEX
760 280 8A A6 68 1C1 2E F2 0 3B0 10A 0 271 5A 1E0 0
HEX
9A0 320 B6 CE B4 255 20 D8 0 370 42 0 2DF 56 258 0
HEX
900 320 AA CA 9A 20D 29 FC 0 3C0 8C 0 2EE 5F 258 0
1-12
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table 1-6. Auto-Configuration Modes 4-7--YCrCb Input (2 of 2) Mode 4 Mode 5 NTSC 640x480 PAL 640x480 CLKO=28.195793 MHz CLKO=29.500008 MHz DEC
YLPF [1:0] V_SCALE [13:0] PLL_FRACT [15:0] EN_XCLK BY_PLL PLL_INT [5:0] EN_SCART ECLIP PAL DIS_SCRESET VSYNC_DUR 625LINE SETUP NI_OUT SYNC_AMP [7:0] BST_AMP [7:0] MCR [7:0] MCB [7:0] MY [7:0] MSC [31:0] 3 5266 34830 0 0 12 0 0 0 0 1 0 1 0 229 118 121 68 133
1.0 Functional Description
1.3 Circuit Description
Register Name
Mode 6 NTSC 800x600 CLKO=38.769241 MHz DEC
3 7373 15124 0 0 17 0 0 0 0 1 0 1 0 229 116 119 67 133 396552378
Mode 7 PAL 800x600 CLKO=36.000000 MHz DEC
3 5734 0 0 0 16 0 0 1 0 0 1 0 0 240 87 128 72 140 528951320
HEX
3 1492 880E 0 0 C 0 0 0 0 1 0 1 0 E5 76 79 44 85
DEC
3 4096 7282 0 0 13 0 0 1 0 0 1 0 0 240 88 129 73 140
HEX
3 1000 1C72 0 0 D 0 0 1 0 0 1 0 0 F0 58 81 49 8C
HEX
3 1CCD 3B14 0 0 11 0 0 0 0 1 0 1 0 E5 74 77 43 85 17A2E8BA
HEX
3 1666 0 0 0 10 0 0 1 0 0 1 0 0 F0 57 80 48 8C 1F872818
545259520 20800000 645499916 26798C0C
1.3.6 Clocking and Timing Generation
There are two timing generators that control the operation of the encoder. The encoder timing block generates the signals for the proper encoding of the video into NTSC or PAL, and extracts the processed input pixels from the internal FIFO. The encoding timing generator can receive its clock from either an external crystal oscillator and PLL, or from the CLKI pin. Normal operation requires that the encoding clock be generated by the PLL. The clock source is selected by the EN_XCLK register bit. If EN_XCLK is set to a logical 0, the internal clock source is selected; and when the EN_OUT bit is set, the CLKO pin is enabled to drive the derived clock. A crystal must be present between XTALIN and XTALOUT pins if the internal clock source is selected. The frequency of the CLK is synthesized by a PLL such that the frequency is: Fclk = Fxtal * {PLL_INT(5:0) + [PLL_FRACT(15:0)/216]}/6
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1.0 Functional Description
1.3 Circuit Description
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
The crystal must be chosen so that the precise line rate for the video standards required can be achieved. This is done to maintain the subcarrier relationship to the line rate and thereby achieve the precise subcarrier frequency as required by the standard. The crystal oscillator is designed to oscillate from 5-25 MHz. A 13.5 MHz crystal meets the requirements for both NTSC and PAL video standards. The crystal must be within 50 ppm of the maximum desired clock rate for NTSC operation, and 25 ppm for PAL operation, across temperature (0 to 70C). See Appendix B for list of recommended crystal vendors. The crystal oscillator is disabled by the SLEEP pin. Sufficient time (greater than approximately 1 second) must be allowed after coming out of sleep mode to allow the oscillator to stabilize. If the external clock source is selected (EN_XCLK=1), a clock signal of the desired pixel clock rate must be present at the CLKI pin. The CLKO pin will be three-state, and the crystal oscillator disabled. The clock must meet the same requirements as above. It is highly recommended that the internal clock be used in order to ensure that the output video remain within the specifications defined by the relevant video standard. Any aberration in the source clock is reflected in the output video and detracts from the quality of the image. The BY_PLL bit will bypass the PLL, and the encoder clock will be at the crystal frequency. This bit will take precedence over the EN_XCLK bit. The second timing generator controls the generation of the HSYNC*, VSYNC*, BLANK*, and pixel input clocking. This is normally the same clock as the encoding clock. The EN_ASYNC register bit, if set, will allow this clock to be driven directly by the CLKI pin. If the DIV2 register bit is set, this internal clock is divided by two before driving the second timing generator. This is required for interlaced input to interlaced output mode (i.e., CCIR601 applications). The CLKI pin is the clock used for synchronizing the pixel inputs (P[23:0]) and any timing input signals (HSYNC*, VSYNC*, and BLANK*) and normally must be a delayed version of the CLKO pin. It can be directly connected to CLKO if desired. Data is registered with this input and re-synchronized to the internal clock. Normally, in muxed input mode, both edges of the CLKI input are used. If the MODE2X register bit is set, the internal clock is divided by two, allowing a 2x external clock, and the data to be provided on the rising edge only.
1.3.7 Master and Slave Modes
The device can operate as either a timing master or a slave. In master mode, the device will generate and output HSYNC*, VSYNC*, and BLANK*. In slave mode, these must be provided externally. The desired mode is selected by the SLAVE pin and SLAVER bit. It is highly recommended that the device operate as a master, to ensure that the input and output video streams remain synchronized. If the device supplying the HSYNC* and VSYNC* inputs in slave mode is not correctly programmed, or the timing varies from that which is required, the output image will lose lock with the input. By running the device in master mode, any timing errors that occur can be absorbed to some extent by the on-board FIFO.
1-14
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
1.0 Functional Description
1.3 Circuit Description
1.3.8 Input Formats
The device can convert a wide range of input formats to television video formats. The input format can be either non-interlaced computer video in 640 x 480 or 800 x 600 formats, or interlaced formats such as CCIR601 formats as well as most other formats which might be encountered. For detailed information on the CCIR601 mode, please refer to the "DVD Movie Playback Architecture and Solutions Application Note". This application note may be obtained from your local Conexant Semiconductor sales office.
1.3.9 Pixel Input Timing
The device can accept the input in data either RGB or YCrCb color spaces. Data can be input either a full pixel at a time, clocked in on the rising edge of CLKI, or in various multiplexed modes, using both edges of CLKI. In YCrCb mode, either 24-bit 4:4:4 data or 16-bit 4:2:2 data can be input. In RGB mode, either 15 bit 5:5:5, 16 bit 5:6:5, or 24-bit RGB can be input. In 16-bit 4:2:2 YCrCb input mode, multiplexed Y, Cr, and Cb data is input through the P[11:4] inputs. The Y data is input on the falling edge of CLK. The Cr/Cb data is input on the rising edge of CLK. The Cb/Y/Cr/Y sequence begins at the first active pixel. In 24-bit 4:4:4 YCrCb input mode, multiplexed Y, Cr, and Cb data is input through the P[11:0] inputs. The input data is sampled on both the rising and falling edge of CLK. In RGB input mode, input data is sampled as 12 bits in 24-bit RGB mode or 8 bits in 15/16 bit RGB mode on both the rising and falling edge of CLK. Table 1-2 shows the assignments of input P[11:0] data on rising edge and falling edge of CLK. In addition, all 24-bit modes can utilize a non-multiplexed mode. See Table 1-3 on page 1-5.
1.3.10 Output Modes
The encoder can generate the video as Composite/Y-C, as YUV component, or as VGA-style RGB. These modes are selected by the OUT_MODE[1:0] register bits. When outputting RGB, the device will output VGA/SVGA analog RGB. In this mode, the R, G, and B input data is fed to the DACs after the addition of sync and, if the SETUP bit is set, setup. The output currents are scaled so that the DACs output the proper 1 V full-scale levels for driving a monitor. The graphics controller provides all the timing control for the monitor, and the device operates as a slave. Only the P[23:0], BLANK*, HSYNC*, and VSYNC* input pins and the RGB analog output pins are active. The BLANK*, HSYNC*, and VSYNC* pins are automatically enabled as inputs in this mode. Each of the three video signals generated by the OUT_MODE bits can be multiplexed to any DAC using the OUT_MUXA[1:0], OUT_MUXB[1:0], and OUT_MUXC[1:0] register bits.
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1.0 Functional Description
1.3 Circuit Description
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
1.3.11 YCrCb Inputs
Y has a nominal range of 16-235; Cb and Cr have a nominal range of 16-240, with 128 equal to zero. Values of 0 and 255 are interpreted as 1 and 254, respectively. Y values of 1-15 and 236-254, and CrCb values of 1-15 and 241-254, are interpreted as valid linear values. Figure 1-4 shows the frequency response of the sub-sampling process. If 4:4:4 data is input, it is sub-sampled to 4:2:2 prior to overscan compensation and flicker filtering.
Figure 1-4. Decimation Filter at Fs=27 MHz
Chroma Decimation Filter
Decibels (dB)
Freq (Fs=27MHz
The resulting 4:2:2 output must then be converted to YUV values and then scaled for the output range of the DACs. The MY, MCR, and MCB registers must be programmed to perform this conversion. The scaling equations are as follows: MY = (int) [V100/(219.0 * VFS) * 26 + 0.5] MCR = (int)[(128.0/127.0) * V100 * 0.877/(224.0 * VFS * 0.713 * sinx) * 26 + 0.5] MCB = (int)[(128.0/127.0)* V100 * 0.493/(224.0 * VFS * 0.564 * sinx) * 26 + 0.5] where:V100 = 100% white voltage (0.661 V for NTSC, 0.7 V for PAL) VFS = Full scale output voltage (1.28 V) SINX = SIN (2 FSC/FCLK)/(2 FSC/FCLK)
1-16
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
1.0 Functional Description
1.3 Circuit Description
1.3.12 RGB Inputs
With IN_MODE set to 24, 16, or 15-bit RGB mode, digital, gamma-corrected RGB data with a 0-255 range is input via the P[11:0] inputs in 24-bit RGB mode or P[11:4] inputs in 15/16-bit RGB mode on both the rising and falling edge of CLK. The RGB data is converted to Y/R-Y/B-Y as follows: Y[9:0] = [INT(.299 * 210) * R[7:0] + INT(.587 * 210) * G[7:0] + INT(.114 * 210) * B[7:0] = 27] * 2-8, 0 to 1024 The Y/R-Y/B-Y values are then sub-sampled to 4:2:2 data prior to overscan compensation and flicker filtering. The resulting 4:2:2 output must then be converted to YUV values and then scaled for the output range of the DACs. The MY, MCR, and MCB registers must be programmed to perform this conversion. The scaling equations are as follows: MY = (int)[V100/(255 * VFS)*26 + 0.5] MCR = (int)[(128.0/127.0) * V100 * 0.877/(127 * VFS * sinx) * 25 + 0.5] MCB = (int)[(128.0/127.0) * V100 * 0.493/(127 * VFS * sinx) * 25 + 0.5] where:V100 = 100% white voltage (0.661 V for NTSC, 0.7 V for PAL) VFS = Full scale output voltage (1.28 V) SINX = SIN (2 FSC/FCLK)/(2 FSC/FCLK)
1.3.13 Video Amplitude Scaling
Both the luminance and chrominance video amplitudes can be scaled by the MCR, MCB, and MY registers. This allows various colormetry standards to be achieved, and can also be used to boost the chroma to compensate for the sinX/X loss of the DACs. Tables 1-7 and 1-8 show the range of values achievable and values for various video formats.
Table 1-7. Video Modes Mode
VSYNC_DUR 625LINE SETUP PAL
NTSC
1 0 1 0
NTSC-Japan
1 0 0 0
PAL-BDGHI
0 1 0 1
PAL-N
1 1 1 1
PAL-Nc
0 1 0 1
PAL-M
1 0 1 1
PAL-60
1 0 0 1
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1.0 Functional Description
1.3 Circuit Description
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Table 1-8. Video Levels Mode
100% White Amp (V) Sync Amp (V) Subcarrier Amp (V) YCrCb Input MY MCR MCB RGB Input MY MCR MCB SYNC_AMP BST_AMP 0-255 0-255 0-255 0-255 0-255 0-255 0-255 0-255
Range
NTSC
0.661 0.286 0.286 153 187 133 133 117 66 225 114
NTSCJapan
0.714 0.286 0.286 158 207 149 143 127 71 225 114
PALBDGHI
0.7 0.301 0.3 158 207 149 141 124 70 238 90
PAL-N
0.661 0.286 0.3 153 187 133 133 117 66 225 90
PAL-Nc
0.7 0.301 0.3 158 207 149 141 124 70 238 90
PAL-M
0.661 0.286 0.306 153 187 133 133 117 66 225 92
PAL-60
0.7 0.301 0.306 158 207 149 141 124 70 238 92
1.3.14 Input Pixel Horizontal Sync
The HSYNC* pin provides the pixel synchronization for the pixel input data. It is an output in master mode, and an input in slave mode. In master mode, it is a pulse two CLK cycles in duration whose leading edge indicates the beginning of a new line of pixel data. The period of the pulses is H_CLKI CLK cycles. The first pixel should be presented to the device H_BLANKI minus the internal pipelined clock (in CLK cycles) after a leading edge of HSYNC*. The next H_ACTIVE pixels will be accepted as active pixels and used in the construction of the output video. In slave mode, the period must be exactly the number of clocks required for the desired overscan mode. Only the leading edge is used, and the high and low times must be at least two CLK cycles in duration. HSYNC* is clocked by the rising edge of CLKI. HSYNCI is clocked by the rising edge of CLKI. The polarity of the HSYNC* pin can be programmed by the HSYNCI register bit. The default convention is active low.
1-18
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
1.0 Functional Description
1.3 Circuit Description
1.3.15 Input Pixel Vertical Sync
The VSYNC* pin provides the line synchronization for the pixel input data. It is an output in master mode, and an input in slave mode. For non-interlaced input timing in master mode, VSYNC* is a pulse one horizontal line time in duration whose leading edge indicates the beginning of a frame of input pixel data. The leading edge coincides with the leading edge of HSYNC*. The period of the pulses is V_LINESI horizontal lines. The first line of data should be presented to the device V_BLANKI lines after the leading edge of VSYNC*. The next V_ACTIVEI lines are accepted as active lines and used in the construction of the output video. In slave mode, the period must be exactly the frame rate of the desired video format. Only the leading edge is used, and the high and low duration must be at least two CLK cycles. The beginning of the frame of data is indicated by the next leading edge of HSYNC* coincident with or after the leading edge of VSYNC*. For interlaced input timing, only slave mode is supported. The period must be exactly the frame rate of the desired video format. If the leading edge of HSYNC* and VSYNC* are coincident, which indicates the input is in odd field, the internal line counter is reset to line 1 at the leading edge of VSYNC*. If the leading edges of HSYNC* and VSYNC* are not coincident, which indicates the input is in even field, the internal line counter will be reset to line 2 at the beginning of the next line. Only the leading edge of VSYNC* is used, and the high and low duration must be at least two CLK cycles. VSYNC* is clocked by the rising edge of CLKI. The polarity of the VSYNC* output can be programmed by the VSYNCI register bit. The default convention is active low.
1.3.16 Input Pixel Blanking
The input pixel blanking can be controlled by either the BLANK* pin or by the internal registers. It can be programmed independently of master/slave mode using the EN_BLANKO register bit. In output mode (EN_BLANKO=1), the pixel blanking is generated based on the active area defined by the H_BLANKI, H_ACTIVE, V_BLANKI, and V_ACTIVEI registers, and the BLANK* pin will be output in the proper relationship to the syncs to indicate the active pixels. In input mode (EN_BLANKO=0), when the BLANK* pin goes high, it will indicate start of active pixels at the pixel input pins. The duration of active pixel is still determined by the H_ACTIVE register. BLANK* is clocked by the rising edge of CLKI. An additional function for the BLANK* pin is used if the EN_DOT register bit is set. In this mode, the internally-generated blanking is used. The BLANK* pin becomes an input whose rising edge defines the graphics controller character clock boundary. This is used internally by the encoder to keep track of the exact pixel count for controllers that cannot operate at pixel clock rates but instead operate at VGA character clock rates.
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1.0 Functional Description
1.3 Circuit Description
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
1.3.17 Overscan Compensation and Flicker Filtering
The resulting subsampled and optionally color-space-converted pixel data is processed by the overscan compensation and flicker filtering logic. This process converts the lines of input pixel data to the appropriate number of output lines for producing a full-screen image on the television receiver. The image, which is 100% within the viewable area of the screen (overscan compensated), can perform vertical filtering to reduce the effects of picture flicker due to the interlacing of the output image. The amount of flicker filtering is programmable, because this process trades off vertical resolution in order to reduce the flicker, and allows the process to be optimized for the image. Horizontal scaling is achieved by adjusting the encoder clock rate. No additional horizontal processing is performed on the input pixels. This allows the full bandwidth of the input image to be output, limited only by the 2x upsampling filter response, which is nominally greater than 6 MHz. The device can accept a wide variety of input image formats, from 640x480 to 800x600, and can output all NTSC and PAL video formats. Figures A-1 through A-4 in Appendix A show the possible ranges of overscan compensation for 640x480 and 800x600 NTSC and PAL formats, for graphics controllers with synchronization resolutions of 1, 8, and 9 pixel clocks, using a horizontal blanking interval of 20 pixel clocks. Tables A-3 through A-10 show representative values for the following: * * Input picture and frame and output picture and field sizes for 640x480 and 800x600 input picture size NTSC and PAL outputs using a horizontal blanking interval of 2.5 s.
The DIS_FFILT register bit disables the flicker filter. The vertical scaling should also be disabled by setting the VSCALE register to 4096 for non-interlaced input, or 0 for interlaced input. CONFIG[2:0] This field determines the configuration for the automatic configuration process. 000 = NTSC 640 x 480 RGB input 001 = PAL 640 x 480 RGB input 010 = NTSC 800 x 600 RGB input 011 = PAL 800 x 600 RGB input 100 = NTSC 640 x 480 YCrCbYCrCb input 101 = PAL 640 x 480 YCrCb input 110 = NTSC 800 x 600 YCrCb input 111 = PAL 800 x 600 YCrCb input
LUMADLY[1:0] This 2-bit value can be used to program the luminance delay in pixels for the CVBS_DLY and Y_DLY output modes. 00 = no delay 01 = 1 pixel 10 = 2 pixels 11 = 3 pixels
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BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
1.0 Functional Description
1.3 Circuit Description
1.3.18 VGA Compatibility
To achieve VGA compatibility, the controller must manipulate the VGA register settings in order to produce a consistent output timing for all VGA modes. The encoder has no way of knowing that a different VGA mode has been selected, and therefore cannot make any adjustments to the timing. The extent of VGA compatibility is entirely the controller's responsibility.
1.3.19 Analog Horizontal Sync
The duration of the horizontal sync pulse is determined by the horizontal sync width register (HSYNC_WIDTH[7:0]). The beginning of the horizontal sync pulse corresponds to the reset of the internal horizontal pixel counter. The horizontal line rate is determined by H_CLKI[11:0]. The internal horizontal counter is reset to 1 at the beginning of the horizontal sync and counts up to H_CLKI. The sync rise and fall times are automatically controlled. The sync amplitude is programmable over a range of values by SYNC_AMP[7:0]. Table 1-8 lists the range of sync values obtainable and the preferred values for various video formats.
1.3.20 Analog Vertical Sync
The duration of the vertical sync is selectable as either 2.5 or 3 lines by register bit VSYNC_DUR. If VSYNC_DUR = 0, 3 lines are selected; if VSYNC_DUR = 1, 2.5 lines are selected. The duration of the serration and equalization pulses are 1/2 the duration of the horizontal sync duration.
1.3.21 Analog Video Blanking
Analog video blanking is controlled by the H_BLANKO, V_BLANKO, and V_ACTIVEO registers. Together they define an active region where pixels will be displayed. V_BLANKO defines the number of lines from the leading edge of the analog vertical sync to the first active output lines, per field; V_ACTIVEO defines the number of active output lines. H_BLANKO defines the number of output pixels from the leading edge of horizontal sync to the first active output pixel; H_BLANKO defines the number of active output pixels. The device will automatically blank the video from the start of the horizontal sync interval through the end of the burst, as well as the vertical sync to prevent erroneous video timing generation.
1.3.22 Video Standards
There are several bits (625LINE, SETUP, and VSYNC_DUR) and a PAL pin that control the generation of various video standards. (These are summarized in Table A-1.) They allow the generation of all the NTSC and PAL video standards. These bits control the specific encoding process parameter, and other registers may also need to be modified to meet all the video parameters of the particular video standard. Video timing diagrams are illustrated in Figures 1-5 through 1-13, which summarize all the common video standards and the required register values for typical input formats.
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1.0 Functional Description
1.3 Circuit Description
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Figure 1-5. Interlaced 525-Line (NTSC) Video Timing
RESET* Start of VSYNC
Analog FIELD 1
523
524
525
1
2
3
4
5
6
7
8
9
10
22
BURST PHASE Analog FIELD 2
261
262
263
264
265
266
267
268
269
270
271
272
285
Analog FIELD 3
523
524
525
1
2
3
4
5
6
7
8
9
10
22
BURST PHASE Analog FIELD 4
261
262
263
264
265
266
267
268
269
270
271
272
285
Burst Begins with Positive Half-Cycle Burst Phase = Reference Phase = 180 Relative to B-Y Burst Begins with Negative Half-Cycle Burst Phase = Reference Phase = 180 Relative to B-Y
NOTE(S): SMPTE line numbering convention is used rather than CCIR624.
1-22
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BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Figure 1-6. Interlaced 525-Line (PAL-M) Video Timing
1.0 Functional Description
1.3 Circuit Description
RESET* Start of VSYNC*
Analog FIELD 1
523
524
525
1
2
3
4
5
6
7
8
9
10
11
12
22
Burst Phase Analog FIELD 2
261
262
263
264
265
266
267
268
269
270
271
272
273
274
285
Analog FIELD 3
523
524
525
1
2
3
4
5
6
7
8
9
10
11
12
22
Burst Phase Analog FIELD 4
261
262
263
264
265
266
267
268
269
270
271
272
273
274
285
Burst Phase = Reference Phase = 135 Relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90 = 225 Relative to U PAL Switch = 1, -V Component
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1.0 Functional Description
1.3 Circuit Description
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Figure 1-7. Interlaced 625-Line (PAL-B, D, G, H, I, Nc) Video Timing (Fields 1-4)
RESET*
Start of VSYNC Analog FIELD 1
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
- U PHASE Analog FIELD 2
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog FIELD 3
620
621
622
623
624
625
1
2 Analog FIELD 4
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
FIELD One Burst Blanking Intervals FIELD Two FIELD Three FIELD Four
Burst Phase = Reference Phase = 135 Relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90 = 225 Relative to U PAL Switch = 1, -V Component
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BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Figure 1-8. Interlaced 625-Line (PAL-B, D, G, H, I, Nc) Video Timing (Fields 5-8)
RESET* Start of VSYNC Analog FIELD 5
1.0 Functional Description
1.3 Circuit Description
620
621
622
623
624
625
1
2 - U PHASE Analog FIELD 6
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog FIELD 7
620
621
622
623
624
625
1
2 Analog FIELD 8
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
FIELD Five Burst Blanking Intervals FIELD Six FIELD Seven FIELD Eight
Burst Phase = Reference Phase = 135 Relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90 = 225 Relative to U PAL Switch = 1, -V Component
100123B
Conexant
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1.0 Functional Description
1.3 Circuit Description
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Figure 1-9. Interlaced 625-Line (PAL-N) Video Timing (Fields 1-4)
VSYNC* Analog FIELD 1 RESET*
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
- U PHASE Analog FIELD 2
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog FIELD 3
620
621
622
623
624
625
1
2 Analog FIELD 4
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
FIELD One Burst Blanking Intervals FIELD Two FIELD Three FIELD Four
Burst Phase = Reference Phase = 135 Relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90 = 225 Relative to U PAL Switch = 1, -V Component
1-26
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Figure 1-10. Interlaced 625-Line (PAL-N) Video Timing (Fields 5-8)
1.0 Functional Description
1.3 Circuit Description
VSYNC* Analog FIELD 5
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
- U PHASE Analog FIELD 6
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog FIELD 7
620
621
622
623
624
625
1
2 Analog FIELD 8
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
FIELD Five Burst Blanking Intervals FIELD Six FIELD Seven FIELD Eight
Burst Phase = Reference Phase = 135 Relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90 = 225 Relative to U PAL Switch = 1, -V Component
100123B
Conexant
1-27
1.0 Functional Description
1.3 Circuit Description
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Figure 1-11. Noninterlaced 262-Line (NTSC) Video Timing
START of VSYNC
261
262
1
2
3
4
5 FIELD 1
6
7
8
9
10
21
START of VSYNC
523
524
263
264
265
266
267
268
269
270
271
272
285
FIELD 2
Burst Begins with Positive Half-Cycle Burst Phase = Reference Phase = 180 Relative to B-Y Burst Begins with Negative Half-Cycle Burst Phase = Reference Phase = 180 Relative to B-Y
Figure 1-12. Noninterlaced 262-Line (PAL-M) Video Timing
START of VSYNC
524
525
1
2
3
4
5 FIELD 1
6
7
8
9
10
11
12
21
START of VSYNC
262
263
264
265
266
267
268 FIELD 2
269
270
271
272
273
274
285
Burst Begins with Positive Half-Cycle Burst Phase = Reference Phase = 180 Relative to B-Y Burst Begins with Negative Half-Cycle Burst Phase = Reference Phase = 180 Relative to B-Y
1-28
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Figure 1-13. Noninterlaced 312-Line (PAL-B, D, G, H, I, N, Nc) Video Timing
1.0 Functional Description
1.3 Circuit Description
RESET* Start of VSYNC
308
309
310
311
312
1
2
3
4
5
6
7
23
24
308
309
310
311
312
1
2
3
4
5
6
7
23
24
Burst Phase = Reference Phase = 135 Relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90 = 225 Relative to U PAL Switch = 1, -V Component
1.3.23 Subcarrier Generation
The device uses a 32-bit-word to synthesize the subcarrier. The value of the subcarrier increment required to generate the desired subcarrier frequency is found with the following equation: MSC[31:0] = (int) (232 * Fsc / Fclk + 0.5) or more directly, for NTSC: MSC[31:0] = 232 * [455 * / (2 * H_CLKO)] and for PAL: MSC[31:0] = 232 * [(1135/4 + 1/625) / (H_CLKO)] where Fclk is the encoder clock rate. This allows the generation of any desired subcarrier to enable the generation of any desired video standard. The 32-bit subcarrier increment MSC[31:0] must be loaded by the serial interface before the subcarrier can be enabled. The device is reset to disable chroma until the last byte of the 32-bit increment is loaded, at which time the chroma will be enabled, unless the DCHROMA bit is set. In order to prevent any residual errors from accumulating, the subcarrier DTO (Discrete Time Oscillator) is reset every four fields for NTSC formats and every eight fields for PAL formats.
100123B
Conexant
1-29
1.0 Functional Description
1.3 Circuit Description
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
1.3.24 Burst Generation
The subcarrier burst generation is a function of the video standard (e.g. NTSC or PAL), the subcarrier frequency increment (MSC[31:03]), and the burst horizontal begin and end register settings (HBURST_BEGIN[7:0] and HBURST_END[7:0]). The value of HBURST_BEGIN[7:0] and HBURST_END[7:0] is the desired pixel minus a value of 128. The burst will automatically be blanked during the horizontal sync to prevent invalid sync pulses from being generated. The burst blanking is automatically controlled by the selected video format. The burst rise and fall times are automatically generated by the device. The burst amplitude can be programmed by BST_AMP[5:0]. Table 1-8 shows the ranges of burst values obtainable and the preferred values for various video formats.
1.3.25 Chrominance Disable
The chrominance subcarrier can be turned off by setting the DCHROMA bit to a logical 1. This kills burst as well, providing luminance-only signals on the CVBS output and a static blank level on the C/R output.
1.3.26 Digital Processing
Once the input data is converted into internal YUV format, the UV components are low-pass filtered with a filter response illustrated in Figure 1-14 (linearly scalable by clock frequency). The Y and filtered UV components are upsampled to CLK frequency by a digital filter whose response is illustrated in Figure 1-15.
Figure 1-14. Three-Stage Chroma Filter
5 0 -5 - 10 - 15 - 20 - 25 - 30 - 35 - 40 0 0.5 1 1.5 Frequency MHz CLK = 27 MHz 2
Attenuation dB
1-30
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Figure 1-15. Luminance Upsampling Filter Response
5 0 -5 - 10 Attenuation dB - 15 - 20 - 25 - 30 - 35 - 40 0 2 4
1.0 Functional Description
1.3 Circuit Description
6 8 10 12 Frequency MHz (Internal Encoder CLK = 27 MHz)
1.3.27 Subcarrier Phasing
In order to maintain correct SC-H phasing, subcarrier phase is set to 0 on the leading edge of the analog vertical sync every four (NTSC) or eight (PAL) fields, unless the DIS_SCRESET bit is set to a logical 1. This is true for both interlaced and non-interlaced outputs. The subcarrier phase can be adjusted from the nominal 0 phase by the PHASE_OFF[7:0] register, where each LSB change corresponds to a 360/256 degree change in the phase. Setting DIS_SCRESET to 1 may be useful in situations where the ratio of CLK/2 to HSYNC* edges in a color frame is noninteger, which could produce a significant phase impulse by resetting to 0.
1.3.28 Noninterlaced Operation
When the BT868/869 is programmed for noninterlaced master mode, it always displays the odd field. FIELD will change state on the leading edge of the analog vertical sync. A 30 Hz offset should be subtracted from the color subcarrier frequency while in NTSC mode so that the color subcarrier phase will be inverted from field to field. Transition from interlaced to noninterlaced in master mode occurs during odd fields to prevent synchronization disturbance.
NOTE:
Consumer VCRs can record noninterlaced video with minor noise artifacts, but special effects (e.g., scan > 2x) may not function properly.
100123B
Conexant
1-31
1.0 Functional Description
1.3 Circuit Description
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
1.3.29 Closed Captioning
The BT868/869 encodes NTSC/PAL-M closed captioning on scan line 21, and NTSC/PAL-M extended data services on scan line 284. Four 8-bit registers (CCF1B1, CCF1B2, CCF2B1, and CCF2B2) provide the data while bits ECCF1 and ECCF2 enable display of the data. A logical 0 corresponds to the blanking level of 0 IRE, while a logical 1 corresponds to 50 IRE above the blanking level. Closed captioning for PAL-B, D, G, H, I, N, Nc is similar to that for NTSC. Closed-caption (CC) encoding is performed for 625-line systems according to the system proposed by the National Captioning Institute; clock and data timing is identical to that of NTSC system, except that encoding is provided on lines 22 and 335, for closed captioning and extended data services respectively. The BT868/869 generates the clock run-in and appropriate timing automatically. Pixel inputs are ignored during CC encoding. See FCC Code of Federal Regulations (CFR) 47 Section 15.119 (10/91 edition or later) for programming information. EIA608 describes ancillary data applications for Field 2 Line 21 (line 284). When CCF1B2 is written, CCSTAT_O is set; when CCF2B2 is written, CCSTAT_E is set. After the CC bytes for the odd field are encoded, CCSTAT_O is cleared; after the CC bytes for the even field are encoded, CCSTAT_E is cleared. If the ECCGATE bit is set, no further encoding will be performed until the appropriate registers are again written; a null will be transmitted on the appropriate CC line in that case. If the ECCGATE bit is not set, the user must rewrite the CC registers prior to reaching the CC line; otherwise the last bytes will be re-encoded. The CC data bytes are double-buffered to prevent loss of data during the encoding process.
1.3.30 Internal Color Bars
The BT868/869 can be configured to generate 100% amplitude, 75% saturation (100/7.5/75/7.5 for NTSC/PAL-M with setup, 100/0/75/0 for PAL) color bars. Color bars can be enabled or disabled by setting the ECBAR bit to a logical 1. The device uses the H_BLANKO register value to determine the starting point of the color bars, and the H_ACTIVE register value to determine the width. Eight bars are displayed, with the colors and amplitudes being generated internally. The pixel inputs are ignored in color bar mode. The MY, MCR, and MCB registers must be programmed for RGB inputs prior to color bar operation.
1.3.31 Macrovision Encoding
The Bt869 device supports Version 7.xx of the Macrovision specification for copy protection for all NTSC and PAL modes. The BT868 does not support the Macrovision feature.
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Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
1.0 Functional Description
1.3 Circuit Description
1.3.32 Outputs
There are four modes for the analog outputs, selected by OUT_MODE[1:0]. The first mode (OUT_MODE=0) generates Composite video (CVBS), Luma (Y), Chroma (C), and Delayed Luma (Y_DLY). The second mode (OUT_MODE=1) generates Luma-Delayed Composite video (CVBS_DLY), Luma (Y), Chroma (C), and Delayed Luma (Y_DLY). The third mode (OUT_MODE=2) generates Component YUV and Delayed Luma (Y_DLY). The fourth mode (OUT_MODE=3) generates VGA-style RGB outputs. The LUMADLY[1:0] register bits control the amount of delay for the delayed luma, from 0 to 3 pixel clocks. For each mode, any of the four generated outputs can be muxed to any of three output DACs by the register bits OUT_MUXA[1:0], OUT_MUXB[1:0], and OUT_MUXC[1:0]. All digital-to-analog converters are designed to drive standard video levels into a combined RLOAD of 37.5 (doubly-terminated 75 ). Unused outputs should be disabled by setting the corresponding DACDISX bit to minimize supply current, or connected directly to ground to minimize supply switching currents.
1.3.33 Output Connection Status
The device can determine whether or not the DAC output is connected to a monitor by verifying that the output is doubly-terminated. The MONSTATx bit for the corresponding DAC is set to a 1 if the device senses a doubly-terminated load on a reset condition or if the CHECK_STAT register bit is set. While CHECK_STAT is set, the output is forced to 2/3 of VREF when terminated and 4/3 of VREF if unterminated. The MONSTATx bit reflects the condition when the DAC output is less than or equal to VREF. The CHECK_STAT bit is automatically cleared after two clock cycles.
1.3.34 Output Filtering and SINX/X Compensation
The DAC output response is a typical sinx/x response. For the composite video output, this results in a slightly lower than desired burst and chroma amplitude value. This can be compensated for, to some extent, by choosing an output filter which boosts higher frequency response slightly. Another method which can be used effectively, and is used by default in the auto configuration modes, is to boost the burst and chroma gain as programmed by the BST_AMP and MCR/MCB register values by x/sinx. The amount of sinx/x amplitude reduction is calculated by: sinx/x = sin ( * Fsc/Fclk) / ( * Fsc/Fclk)
100123B
Conexant
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1.0 Functional Description
1.3 Circuit Description
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
1.3.35 Power-Down Modes
The device can be placed in a low-power mode by the SLEEP pin. In this mode, the analog circuitry is shut down, disabling the output video, and the internal clock to the device is held constant, placing both the analog and digital current draw to a minimum. Register states are preserved, but other chip functionality (including the serial interface) is disabled. This mode achieves the greatest reduction in power. In addition, the entire analog subsection can be powered-down with the DACOFF bit, allowing digital operations to continue while reducing the power in the analog circuitry. This will achieve a significant reduction in power while maintaining all digital functionality. Each individual DAC can also be powered down by its corresponding DACDISx bit. This is useful only if some of the DACs are being used, in order to minimize the power in the system.
1.3.36 Serial Interface
The device includes a 2-wire serial interface which is used for programming the registers in the device. The interface is designed to operate with either 3.3 V or 5 V input levels by changing the supply voltage for the input and output drivers with the VDD_SI pin.
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2
2.0 Internal Registers
A register bit map is displayed in Table 2-1, and a read-back bit map is displayed in Table 2-2. Bit descriptions and detailed programming information follow the bit map. All registers are write-only and are set to 0 following a software reset. A software reset is always performed at power-up; after power-up, a reset can be triggered by writing the SRESET register bit.
Table 2-1. Register Bit Map (1 of 3) 8-Bit Address
6C 6E 70 72 74 76 78 7A 7C 7E 80 82 84 86 88 8A 8C 8E 90 92 94 96
D7
TIMING RESET HSYNOFFSET[7:0] HSYNOFFSET[9:8] VSYNOFFSET[7:0] DATDLY H_CLKO[7:0] H_ACTIVE[7:0] HSYNC_WIDTH[7:0] HBURST_BEGIN[7:0] HBURST_END[7:0] H_BLANKO[7:0] V_BLANKO[7:0] V_ACTIVEO[7:0] V_ACTIVEO[8] H_FRACT[7:0] H_CLKI[7:0] H_BLANKI[7:0] Reserved V_LINESI[7:0] V_BLANKI[7:0] V_ACTIVEI[7:0] CLPF[1:0]
D6
RESERVED
D5
D4
D3
D2
D1
D0
HSYNWIDTH[5:0]
DATSWP
VSYNOFFSET[10:8]
VSYNWIDTH[2:0]
Reserved
H_ACTIVE[9:8]
H_CLKO[11:8]
Reserved
Reserved
VBLANKDLY
H_BLANKI[8]
H_CLKI[10:8]
YLPF[1:0]
V_ACTIVEI[9:8]
V_LINESI[9:8]
100123B
Conexant
2-1
2.0 Internal Registers
BT868/Bt869 Flicker-Free Video Encoder with UltrascaleTM Technology
Table 2-1. Register Bit Map (2 of 3) 8-Bit Address
98 9A 9C 9E A0 A2 A4 A6 A8 AA AC AE B0 B2 B4 B6 B8 BA BC BE C0 C2 C4 C6 C8 CA CC CE D0 D2 D4 SRESET CCF2B1[7:0] CCF2B2[7:0] CCF1B1[7:0] CCF1B2[7:0] ESTATUS[1:0] EN_BLANKO DIS_YFLPF DIS_GMUSHY DIS_GMUSHC Reserved CCR_START[7:0] CC_ADD[7:0] MODE2X DIV2 EN_ASYNC CCR_START[8] CC_ADD[11:8] EN_DOT DIS_FFILT DIS_GMSHY DIS_GMSHC ECCF2 FIELDI F_SELC[2:0] YCORING[2:0] CCORING[2:0] OUT_MUXC[1:0] ECCF1 VSYNCI ECCGATE HSYNCI ECBAR DCHROM A EN_OUT CHECK_STAT SLAVER DACOFF
D7
V_SCALE[7:0] H_BLANKO[9:8] PLL_FRACT[7:0] PLL_FRACT[15:8] EN_XCLK Reserved SYNC_AMP[7:0] BST_AMP[7:0] MCR[7:0] MCB[7:0] MY[7:0] MSC[7:0] MSC[15:8] MSC[23:16] MSC[31:24] PHASE_OFF[7:0]
D6
D5
D4
D3
D2
D1
D0
V_SCALE[13:8]
BY_PLL
PLL_INT[5:0]
ECLIP
PAL_MD
DIS_SCRESET
VSYNC_DU R
625LINE
SETUP
NI_OUT
EN_PINCFG Reserved
CONFIG[2:0] DACDIS C DACDISB DACDISA
IN_MODE[2:0] F_SELY[2:0] YATTENUATE[2:0] CATTENUATE[2:0]
OUT_MUXB[1:0]
OUT_MUXA[1:0]
2-2
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table 2-1. Register Bit Map (3 of 3) 8-Bit Address
D6 D8
2.0 Internal Registers
2.1 Essential Registers
D7
Reserved Reserved
D6
Reserved
D5
Reserved
D4
Reserved
D3
OUT_MODE[1:0]
D2
D1
LUMADLY[1:0]
D0
2.1 Essential Registers
The power-up state is defined to be black burst CCIR601 NTSC video. To enable active video, the EN_OUT register bit must be set. This bit enables CLKO, HSYNC*, VSYNC*, BLANK*, and FIELD outputs. If this bit is not set, then these pins are set to a high impedance.
2.2 Writing Addresses
Following a start condition, writing 0x88 initiates access to subaddresses. Alternative address 0x8A must be written if the ALTADDR pin is high. If the data is written in subaddress order, only the beginning subaddress needs to be written; the internal address counter will automatically increment after each write to a register.
2.3 Reading Information
Following a start condition, writing 0x89 initiates the read-back sequence, during which 8 bits of information can be read from the SID pin, MSB first. Alternative address 0x8B is required if the ALTADDR pin is high. For the case of ESTATUS[1:0]=00 prior to the read sequence, the first three bits indicate the part type (BT868 or Bt869). The lower five bits indicate the version number or the status bits. The instances where ESTATUS[1:0]=01 and ESTATUS[1:0]=10, the bits read back from the VGA Encoder will contain information as specified by Table 2-2. For software detection of a connected TV monitor on each DAC output, ESTATUS[1:0] must equal 01 and the MONSTAT x bits should be read accordingly after writing to CHECK_STAT. Data details are defined in Table 2-3; bit and register definitions are displayed in Table 2-4.
100123B
Conexant
2-3
2.0 Internal Registers
2.3 Reading Information
BT868/Bt869 Flicker-Free Video Encoder with UltrascaleTM Technology
Table 2-2. Read-Back Bit Map
ESTATUS[1:0] 00 01 10 MONSTAT_ A 7 6 ID[2:0] MONSTAT_B MONSTAT_C CCSTAT_E PLL_LOCK 5 4 3 2 VERSION[2:0] CCSTAT_O FIFO_OVER FIELD[2:0] FIFO_UNDER PAL BUSY 1 0
Table 2-3. Data Details Defined Bit Names
ID[2:0] VERSION[4:0] MONSTAT_A MONSTAT_B MONSTAT_C CCSTAT_E CCSTAT_O FIELD[2:0] PLL_LOCK FIFO_OVER FIFO_UNDER PAL BUSY
Data Definition
Indicates the part number: 000 is returned from the BT868; 001 is returned from the Bt869. Version number; for this revision, these bits are 00001. Monitor connection status for DACA output, 1 denotes monitor connected to DACA. Monitor connection status for DACB output, 1 denotes monitor connected to DACB. Monitor connection status for DACC output, 1 denotes monitor connected to DACC. High if closed-caption data has been written for the even field; it is low immediately after the clock run-in on line 21(NTSC) or 22(PAL). High if closed-caption data has been written for the odd field; it is low immediately after the clock run-in on line 284(NTSC) or 335(PAL). Field number, where 000 indicates the first field, 111 indicates the 8th field. High when PLL is locked. Set to one if FIFO overflows. Reset on read. Set to one if FIFO underflows. Reset on read. Indicates status of PAL pin. Indicates that the device is in the process of initializing the registers and that the registers cannot be written. This bit remains high for 512 CLK-0 after an auto configuration cycle begins.
Table 2-4. Programming Detail (1 of 7) Bit/Register Names
H_CLKO[11:0] H_ACTIVE[9:0] HSYNC_WIDTH[7:0] HBURST_BEGIN[7:0] HBURST_END[7:0] H_BLANKO[9:0] V_BLANKO[7:0] V_ACTIVEO[8:0] Number of output CLKs/line Number of active input and output pixels Analog sync width in clocks Beginning of burst 50% point in number of clock cycles from analog hsync falling edge End of burst 50% point in number of clock cycles--128 from analog sync falling edge Number of output CLKs between leading edge of horizontal sync and active video Line number of first active line (number of blank lines + 1) Number of active output lines/field
Bit/Register Definition
2-4
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table 2-4. Programming Detail (2 of 7) Bit/Register Names
H_FRACT[7:0] H_CLKI[10:0] H_BLANKI[8:0] VBLANKDLY V_LINESI[9:0] V_BLANKI[7:0] V_ACTIVEI[9:0] CLPF[1:0]
2.0 Internal Registers
2.3 Reading Information
Bit/Register Definition
Fractional number of input clocks per line Number of clocks per line between successive HSYNC* edges Number of input pixels between HSYNC* leading edge and first active pixel If set, the effective vertical blanking value in the second field is V_BLANKI+1. Number of vertical input lines Number of input lines between VSYNC* leading and first active line Number of active input lines Chroma Horizontal Low Pass Filter 00 = Bypass 01 = Reserved 10 = Chroma Horizontal LPF2 11 = Chroma Horizontal LPF3
YLPF[1:0]
Luma Post-FlickerFilter/Scaler Horizontal Low Pass Filter 00 = Bypass 01 = Luma Horizontal LPF1 10 = Luma Horizontal LPF2 11 = Luma Horizontal LPF3
V_SCALE[13:0] PLL_FRACT[15:0] PLL_INT[5:0] EN_XCLK BY_PLL Reserved ECLIP
Vertical scaling coefficient Fractional portion of PLL multiplier Integer portion of PLL multiplier 0 = Encoder generates pixel clock 1 = Use CLKI pin as pixel clock source 0 = Use PLL 1 = Bypass PLL (encoder clock is crystal frequency) Reserved for future software compatibility; should be set to zero for normal operation. 0 = Normal operation 1 = Enable clipping; DAC values less than 31 are made 31 Video output switch bit. If PAL pin = 0, this controls analog output format 0 = Changes video output to NTSC mode 1 = Changes video output to PAL mode (even if PAL pin = 0) 0 = Normal operation. The subcarrier phase is reset to 0 at the beginning of each color field sequence 1 = Disables subcarrier reset event at beginning of field sequence 0 = Generates 2.5-line VSYNC analog output 1 = Generates 3-line VSYNC analog output 0 = 525-line format 1 = 625-line format 1 = Setup on. The 7.5-IRE setup is enabled for active video lines. 0 = Setup off. The 7.5-IRE setup is disabled for active video lines. 0 = Interlaced analog video output 1 = Noninterlaced analog video output
PAL_MD
DIS_SCRESET
VSYNC_DUR 625LINE SETUP NI_OUT
100123B
Conexant
2-5
2.0 Internal Registers
2.3 Reading Information
BT868/Bt869 Flicker-Free Video Encoder with UltrascaleTM Technology
Table 2-4. Programming Detail (3 of 7) Bit/Register Names
SYNC_AMP[7:0] BST_AMP[7:0] MCR[7:0] MCB[7:0] MY[7:0] MSC[31:0] PHASE_OFF[7:0] EN_PINCFG
Bit/Register Definition
Multiplication factor for sync amplitude Burst amplitude multiplication factor Multiplication factor for CR (or R-Y) component prior to subcarrier modulation Multiplication factor for CB (or B-Y) component prior to subcarrier modulation Multiplication factor for Y component Subcarrier increment Subcarrier phase offset When set, this will enable the auto configuration to be controlled by P[23:21]. Whenever a change is detected on these pins, the mode is reconfigured. This field determines the configuration for the automatic configuration process 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 = NTSC 640x480 RGB input PAL 640x480 RGB input NTSC 800x600 RGB input PAL 800x600 RGB input NTSC 640x480 YCrCb input PAL 640x480 YCrCb input NTSC 800x600 YCrCb input PAL 800x600 YCrCb input
CONFIG[2:0]
SRESET
Writing a 1 to this bit performs a software reset; all registers are reset to 0s unless the CONFIG[2:0] field is non-0; in that case, the automatic configuration process is begun and the BUSY status bit is set. This bit is automatically cleared. Writing a 1 to this bit checks the status of the monitor connections at the DAC output. This is also automatically performed on any reset condition, including a software reset. This bit is automatically cleared. 0 = Normal operation 1 = Disables DAC output current and internal voltage reference. This will limit power consumption to just the digital circuits. 0 = Normal operation 1 = Disables DAC output. Current is set to 0; output will go to 0 V. 0 = Normal operation 1 = Disables DACB output. Current is set to 0; output will go to 0 V. 0 = Normal operation 1 = Disables DACA output. Current is set to 0; output will go to 0 V. This is the first byte of closed-caption information for the even field, line 284 for NTSC or line 335 for PAL. Data is encoded LSB first. This is the second byte of closed-caption information for the even field, line 284 for NTSC or line 335 for PAL. Data is encoded LSB first. This is the first byte of closed-caption information for the odd field, line 21 for NTSC or line 22 for PAL. Data is encoded LSB first. This is the second byte of closed-caption information for the odd field, line 21 for NTSC or line 22 for PAL. Data is encoded LSB first. Serial read-back status bit selection. (See Table 2-2.)
CHECK_STAT
DACOFF
DACDISC DACDISB DACDISA CCF2B1[7:0] CCF2B2[7:0] CCF1B1[7:0] CCF1B2[7:0] ESTATUS[1:0]
2-6
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table 2-4. Programming Detail (4 of 7) Bit/Register Names
ECCF2 ECCF1
2.0 Internal Registers
2.3 Reading Information
Bit/Register Definition
0 = Disables closed-caption encoding on field 2. 1 = Enables closed-caption encoding on field 2. 0 = Disables closed-caption encoding on field 1. 1 = Enables closed-caption encoding on field 1. 0 = Normal closed-caption encoding. 1 = Enables closed-caption encoding constraints. After encoding, future encoding is disabled until a complete pair of new data bytes is received. This prevents encoding of redundant or incomplete data. 0 = Normal operation 1 = Enables color bars. 0 = Normal operation 1 = Blank chroma 0 = Three-states all outputs. 1 = Allows outputs to be enabled (depending upon EN_BLANKO register bit and SLAVE pin). Enables BLANK* pin as an output. Enables dot clock synchronization on BLANK* pin. 0 = Logical 1 on FIELD indicates an even field. 1 = Logical 1 on FIELD indicates an odd field. 0 = Active low VSYNC* 1 = Active high VSYNC* 0 = Active low HSYNC* 1 = Active high HSYNC* Format of pixels at input of encoder: 000 = 24-bit RGB multiplexed 001 = 16-bit RGB multiplexed 010 = 15-bit RGB multiplexed 011 = 24-bit RGB non-multiplexed 100 = 24-bit YCrCb multiplexed 101 = 16-bit YCrCb multiplexed 110 = Reserved 111 = 24-bit YCrCb non-multiplexed
ECCGATE
ECBAR DCHROMA EN_OUT EN_BLANKO EN_DOT FIELDI VSYNCI HSYNCI IN_MODE[2:0]
DIS_YFLPF
Luma Initial Horizontal Low Pass Filter 0 = Enable 1 = Disable
DIS_FFILT F_SELC[2:0]
0 = Enables FlickerFilter 1 = Disables FlickerFilter Chroma FlickerFilter: 000 = 5 Line 001 = 2 Line 010 = 3 Line 011 = 4 Line 100 = Alternate 5 Line 101 = Alternate 5 Line 110 = Alternate 5 Line 111 = Alternate 5 Line
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Conexant
2-7
2.0 Internal Registers
2.3 Reading Information
BT868/Bt869 Flicker-Free Video Encoder with UltrascaleTM Technology
Table 2-4. Programming Detail (5 of 7) Bit/Register Names
F_SELY[2:0] Luma FlickerFilter: 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 = DIS_GMUSHY DIS_GMSHY YCORING[2:0] 5 Line 2 Line 3 Line 4 Line Alternate 5 Line Alternate 5 Line Alternate 5 Line Alternate 5 Line
Bit/Register Definition
0 = Enables Luma Anti-Psuedo Gamma Removal. 1 = Disables Luma Anti-Psuedo Gamma Removal. 0 = Enables Luma Psuedo Gamma Removal. 1 = Disables Luma Psuedo Gamma Removal. Luma Coring: 000 = Bypass 001 = 1/128 of range 010 = 1/64 of range 011 = 1/32 of range 100 = 1/16 of range 101 = 1/8 of range 110 = 1/4 of range 111 = Reserved
YATTENUATE[2:0]
Luma Attenuation 000 = 1.0 gain (no attenuation) 001 = 15/16 gain 010 = 7/8 gain 011 = 3/4 gain 100 = 1/2 gain 101 = 1/4 gain 110 = 1/8 gain 111 = 0 gain (Force Luma to 0)
DIS_GMUSHC DIS_GMSHC CCORING[2:0]
0 = Enables Chroma Anti-Psuedo Gamma Removal. 1 =Disables Chroma Anti-Psuedo Gamma Removal. 0 = Enables Chroma Psuedo Gamma Removal. 1 = Disables Chroma Psuedo Gamma Removal. Chroma Coring: 000 = Bypass 001 = 1/128 of range (+/- 1/256 of range) 010 = 1/64 of range (+/- 1/128 of range) 011 = 1/32 of range (+/- 1/64 of range) 100 = 1/16 of range (+/- 1/32 of range) 101 = 1/8 of range (+/- 1/16 of range) 110 = 1/4 of range (+/- 1/8 of range) 111 = Reserved
2-8
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BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table 2-4. Programming Detail (6 of 7) Bit/Register Names
CATTENUATE[2:0] Chroma Attenuation: 000 = 1.0 gain (No Attenuation) 001 = 15/16 gain 010 = 7/8 gain 011 = 3/4 gain 100 = 1/2 gain 101 = 1/4 gain 110 = 1/8 gain 111 = 0 gain (Force Chroma to 0) 00 = Output Video[0] on DACA 01 = Output Video[1] on DACA 10 = Output Video[2] on DACA 11 = Output Video[3] on DACA 00 = Output Video[0] on DACB 01 = Output Video[1] on DACB 10 = Output Video[2] on DACB 11 = Output Video[3] on DACB 00 = Output Video[0] on DACC 01 = Output Video[1] on DACC 10 = Output Video[2] on DACC 11 = Output Video[3] on DACC
2.0 Internal Registers
2.3 Reading Information
Bit/Register Definition
OUT_MUXA[1:0]
OUT_MUXB[1:0]
OUT_MUXC[1:0]
CCR_START[8:0] CC_ADD[11:0] DIV2 MODE2X EN_ASYNC
Closed-captioning clock run-in start in clock cycles from leading edge of HSYNC* Closed-captioning DTO increment Divides input pixel rate by two (for CCIR601 interlaced timing input. Divides selected input clock by two (allows for 2x rather than double-edge clock input). Set to 0 for normal operation. 00 = Video[0-3] is CVBS/ Y/ C/ Y_DLY 01 = Video[0-3] is CVBS_DLY/ Y/ C/ Y_DLY 10 = Video[0-3] is V/ Y/ U/ Y_DLY 11 = Video[0-3] is R/ G/ B/ X (VGA mode) This 2-bit value can be used to program the luminance delay in pixels for the CVBS_DLY and Y_DLY output modes. 00 = No delay 01 = 1 pixel 10 = 2 pixels 11 = 3 pixels
OUT_MODE[1:0]
LUMADLY[1:0]
HSYNOFFSET[9:0]
A 2s-complement number. The values range from -512 pixels to +511 pixels. This register manipulates the falling edge position of the digital HSYNC output from BT868. The default value is 0 and denotes the standard position of the HSYNC leading edge.
100123B
Conexant
2-9
2.0 Internal Registers
2.3 Reading Information
BT868/Bt869 Flicker-Free Video Encoder with UltrascaleTM Technology
Table 2-4. Programming Detail (7 of 7) Bit/Register Names Bit/Register Definition
A 2s-complement number. The values range from -HCLKI pixels to +HCLKI pixels. This register causes the falling edge position of the BT868's digital VSYNC output to occur earlier (- value) or later (+) in time compared to the standard position for NTSC or PAL. The default value is 0 and denotes the standard position of the VSYNC leading edge. Controls the duration/width of the digital HSYNC output pulse. Value will be hexadecimal and its units are in terms of pixels. A value of 0 is a disallowed condition. The acceptable range is 2 pixels to 3F pixels (=63 decimal). The default value is 2. Controls the width of the VSYNC output pulse. Denotes the number of lines the VSYNC digital signal remains low on field transitions. Value will be hexadecimal value and its units are in terms of lines. A value of 0 is a disallowed condition. The acceptable range is 1 line to (23 -1) lines. The default value is 1. Delays the falling edge pixel data by 1 full clock period when the falling edge data precedes the rising edge data. Ensures that the BT868 moves the falling edge data after the rising edge data. The correct sequence of rising edge data/falling edge data/rising edge data will then be encoded by Buteo. The default value for this bit is 0 because most graphics controllers already transmit data in the expected rising edge data/falling edge data sequence. Swaps the falling edge pixel data with the rising edge pixel data at the input of the pixel port. The default value for this bit is 0 which tells the VGA Encoder to expect an order of rising edge data/falling edge data coming from the graphics controller.
VSYNOFFSET[10:0]
HSYNWIDTH[5:0]
VSYNWIDTH[2:0]
DATDLY
DATSWP
NOTE(S): VSYNWIDTH, HSYNWIDTH, VSYNOFFSET, and HSYNOFFSET are active only when the BT868/869 is in the master
timing mode when the encoder outputs HSYNC and VSYNC pulses. In the slave timing mode, these registers are ignored. VSYNCWIDTH and HSYNCWIDTH should never be set to 0.
2-10
Conexant
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3
3.0 PC Board Considerations
For optimum performance of the BT868/869, proper CMOS layout techniques should be studied in the Bt451/457/458 Evaluation Module Operation and Measurements Application Note (AN-16), before PC board layout is begun. The layout should be optimized for lowest noise on the power and ground planes by providing good decoupling. The trace length between groups of VAA and GND pins should be as short as possible to minimize inductive ringing. A well-designed power distribution network is critical to eliminating digital switching noise. The ground plane must provide a low-impedance return path for the digital circuits. A PC board with a minimum of four layers is recommended, with layers 1 (top) and 4 (bottom) for signals, and layers 2 and 3 for ground and power, respectively.
3.1 Component Placement
Components should be placed as close as possible to the associated pin in order for traces to be connected point to point. The optimum layout enables the BT868/869 to be located close to the power supply connector and the video output connector. For an illustration, see Figure 3-1.
3.2 Power and Ground Planes
For optimum performance, a common digital and analog ground plane and a common digital and analog power plane are recommended. The power plane should provide power to all BT868/869 power pins, reference voltage (Vref) circuitry, and COMP decoupling. The BT868/869 power plane should be connected to the graphics system power plane (VCC) at a single point through a ferrite bead, as illustrated in Figures 3-1 and 3-2. This bead should be located within 3 inches of the BT868/869. The bead provides resistance to switching currents, acting as a resistor at high frequencies. A low-resistance bead should be used, such as Ferroxcube 5659065-3B, Fair-Rite 2723021447, or TDK BF45-4001. See Table 3-1 for a typical parts list for key passive components and Figure 3-3 for a schematic diagram of the recommended layout.
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Conexant
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3.0 PC Board Considerations
3.2 Power and Ground Planes
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Figure 3-1. Power Plane Illustration
Bracket 3V
BT868
Ferrite Bead 3VAA-BT868 o Analog Oscillator o VCC3
Bt decoder
o VCC3 Data
3V
5V
Clocks
TOP
Signals
GND PWR
4 layer board plane order:
PCI or AGP Connector
BOTTOM Signals
3-2
Conexant
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BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Figure 3-2. Connection Diagram for Output Filters and Other Key Passive Components
BT868/869 Power Plane C7 C2-C6 C9 C8 GND L1
3.0 PC Board Considerations
3.2 Power and Ground Planes
VAA
BT868/869
COMP VBIAS VREF
+3.3 V (VCC)
+
C10 C1
Ground (Power Supply Connector) RSET = 75 , 75 , 75 ,
FSADJUST
100 ,1%
1%
1%
1%
DACA DACB DACC VAA P Schottky Diodes DAC Output To Filter Schottky Diodes LPF 22 pF GND 22 pF P P
RF Mod/CVBS LPF LPF To Video Connector
RF Modulator/CVBS Out P Buffer 75 TRAP 1.8 H 82 270 pF 330 pF Audio RF Modulator (1) ZIN = 1 K RF CVBS
1.8 H 270 pF 330 pF
(1)
Some modulators may require AC coupling capacitors (10 F).
Table 3-1. Typical Parts List for Key Passive Components Location
C1-C9 C10 L1 RSET TRAP
Description
0.1 F Ceramic Capacitor 47 F Capacitor Ferrite Bead-Surface Mount 1% Metal Film Resistor Ceramic Resonator Schottky Diodes Erie RPE112Z5U104M50V Mallory CSR13F476KM Fair-Rite 2743021447 Dale CMF-55C
Vendor Part Number
Murata TPSx.xMJ or MB2 (where x.x = sound carrier frequency in MHz) BAT85 (BAT54F Dual) HP 5082-2305 (1N6263) Siemens BAT 64-04 (Dual)
NOTE(S): Vendor numbers are listed only as a guide. Substitution of devices with similar characteristics will not affect
BT868/869 performance.
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3.0 PC Board Considerations
3.2 Power and Ground Planes
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Figure 3-3. Complete BT868/Bt869 Recommended Layout
3-4
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BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
3.0 PC Board Considerations
3.3 Decoupling
3.3 Decoupling
3.3.1 Device Decoupling
For optimum performance, all capacitors should be located as close as possible to the device, and the shortest possible leads (consistent with reliable operation) should be used to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radial lead ceramic capacitors can be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self-resonance above the pixel clock.
3.3.2 Power Supply Decoupling
The best power supply performance is obtained with a 0.1 F ceramic capacitor decoupling each group of VAA pins and each group of VDD pins to GND. The capacitors should be placed as close as possible to the device VAA/VDD pins and GND pins and connected with short, wide traces. The 47 F capacitor shown in Figure 3-2 is for low-frequency power supply ripple; the 0.1 F capacitors are for high-frequency power supply noise rejection. When a linear regulator is used, the proper power-up sequence must be verified to prevent latchup. A linear regulator is recommended to filter the analog power supply if the power supply noise is greater than or equal to 200 mV. This is especially important when a switching power supply is used, and the switching frequency is close to the raster scan frequency. About 5% of the power supply hum and ripple noise less than 1 MHz will couple onto the analog outputs.
3.3.3 COMP Decoupling
The COMP pin must be decoupled to the closest VAA pin, typically with a 0.1 F ceramic capacitor. Low-frequency supply noise will require a larger value. The COMP capacitor must be as close as possible to the COMP and VAA pins. A surface-mount ceramic chip capacitor is preferred for minimal lead inductance. Lead inductance degrades the noise rejection of the circuit. Short, wide traces will also reduce lead inductance.
3.3.4 VREF Decoupling
A 0.1 F ceramic capacitor should be used to decouple this input to GND.
3.3.5 VBIAS Decoupling
A 0.1 f ceramic capacitor should be used to decouple this output to GND.
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3.0 PC Board Considerations
3.4 Signal Interconnect
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
3.4 Signal Interconnect
3.4.1 Digital Signal Interconnect
The digital inputs to the BT868/869 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane or analog output signals. Most of the noise on the analog outputs will be caused by excessive edge rates (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. The digital edge rates should not be faster than necessary, as feedthrough noise is proportional to the digital edge rates. Lower-speed applications will benefit from using lower-speed logic (3-5 ns edge rates) to reduce data-related noise on the analog outputs. Transmission lines will mismatch if the lines do not match the source and destination impedance. This will degrade signal fidelity if the line length reflection time is greater than one-fourth the signal edge time (refer to Application Notes AN-11 and AN-12). Line termination or line-length reduction is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without use of termination. Ringing can be reduced by damping the line with a series resistor (30-300 ). Radiation of digital signals can also be picked up by the analog circuitry. This is prevented by reducing the digital edge rates (rise/fall time), minimizing ringing with damping resistors, and minimizing coupling through PC board capacitance by routing the digital signals at a 90-degree angle to any analog signals. The clock driver and all other digital devices must be adequately decoupled to prevent noise generated by the digital devices from coupling into the analog circuitry.
3.4.2 Analog Signal Interconnect
The BT868/869 should be located as close as possible to the output connectors to minimize noise pickup and reflections caused by impedance mismatch. The analog outputs are susceptible to crosstalk from digital lines; digital traces must not be routed under or adjacent to the analog output traces. To maximize the high-frequency power supply rejection, the video output signals should overlay the ground plane. For maximum performance, the analog video output impedance, cable impedance, and load impedance should be the same. The load resistor connection between the video outputs and GND should be as close as possible to the BT868/869 to minimize reflections. Unused analog outputs should be connected to GND.
3-6
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
3.0 PC Board Considerations
3.5 Applications Information
3.5 Applications Information
3.5.1 Electrostatic Discharge and Latchup Considerations
Correct electrostatic discharge (ESD)-sensitive handling procedures are required to prevent device damage. Device damage can produce symptoms of catastrophic failure or erratic device behavior with leaky inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. DAC power decoupling networks with large time constants should be avoided; they could delay VAA and VDD power to the device. Ferrite beads must be used only for analog power VAA decoupling. Inductors cause a time-constant delay that induces latchup, and should not be substituted for a ferrite bead. Latchup can be prevented by ensuring that all VAA and all GND pins are at the same potential and that the VAA and VDD supply voltage is applied before the signal pin voltages. The correct power-up sequence ensures that any signal pin voltage will never exceed the power supply voltage.
3.5.2 Clock and Subcarrier Stability
The color subcarrier is derived directly from the CLKO (derived from XTALIN/XTALOUT) CLKI when EN_XCLK=1 input, hence any jitter or frequency deviation of CLKO (XTALIN/XTALOUT) or CLKI when EN_XCLK=1 will be transferred directly to the color subcarrier. Jitter within the valid CLKO cycle interval will result in hue noise on the color subcarrier on the order of 0.9-1.6 degrees per nanosecond. Random hue noise can result in degradation in AM/PM noise ratio (typically around 40 dB for consumer media such as Videodiscs and VCRs). Periodic or coherent hue noise can result in differential phase error (which is limited to 10 degrees by FCC cable TV standards). Any frequency deviation of CLKO from nominal will challenge the subcarrier tracking capability of the destination receiver. This may range from a few parts-per-million (ppm) for broadcast equipment to 100 ppm for industrial equipment, to a few hundred ppm for consumer equipment. Greater subcarrier tracking range generally results in poorer subcarrier decoding dynamic range, so that receivers that tolerate jitter and wide subcarrier frequency deviation will introduce more noise in the decoded image. Crystal-based clock sources with a maximum total deviation of 50 ppm (NTSC) or 25 ppm (PAL) across the temperature range of 0C to 70C produce the best results for consumer and industrial applications. In rare cases, temperature-compensated clock sources with tighter tolerances may be warranted for broadcast or more stringent PAL (e.g., type I) applications. Some applications call for maintaining correct Subcarrier-Horizontal (SC-H) phasing for correct color framing. This requires subcarrier coherence within specified tolerances over a four-field interval for 525-line systems or 8 fields for 625-line systems. Any clock interruption (even during vertical blanking interval) which results in mis-registration of the CLKI input or nonstandard pixel counts per line, can result in SC-H excursions outside the NTSC limit of 40 degrees
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3.0 PC Board Considerations
3.5 Applications Information
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
(reference EIA RS170A) or the PAL limit of 20 degrees (reference EBU D23-1984). In slave mode, any deviation exceeding the 50 ppm (NTSC) or 25 ppm (PAL) limits of the number CLKO cycles between HSYNC* falling edges when in slave mode may result in a switch to Master Mode.
3.5.3 Filtering Radio Frequency Modulator Connection
The BT868/869's internal upsampling filter alleviates external filtering requirements by moving significant sampling alias components above 19 MHz and reducing the sinx/x aperture loss up to the filters passband cutoff of 5.75 MHz. While typical chrominance subcarrier decoders can handle the BT868/869 output signals without analog filtering, the higher frequency alias products pose some EMI concerns and may create troublesome images when introduced to a radio frequency (RF) modulator. When the video is presented to an RF modulator, it should be free of energy in the region of the aural subcarrier (4.5 MHz for NTSC, 5.5-6.5 MHz for PAL). Hence some additional frequency traps may be necessary when the video signal contains fundamental or harmonic energy (as from unfiltered character generators) in that region. Where better frequency response flatness is required, some peaking in the analog filter is appropriate to compensate for residual digital filter losses with sufficient margin to tolerate 10% reactive components. A three-pole elliptic filter (one inductor, three capacitors) with a 6.75 MHz passband can provide at least 45 dB attenuation (including sinx/x loss) of frequency components above 20 MHz and provide some flexibility for mild peaking or special traps. An inductor value with a self-resonant frequency above 80 MHz is chosen so that its intrinsic capacitance contributes less than 10% of the total effective circuit value. The inductor itself may induce 1% (0.1 dB) loss. Any additional ferrites introduced for EMI control should have less than 5 impedance below 5 MHz to minimize additional losses. The capacitor to ground at the BT868/869 output pin is compensating for the parasitic capacitance of the chip plus any protection diodes and lumped circuit traces (about 22 pF + 5 pF/diode). Some filter peaking can be accomplished by splitting the 75 source impedance across the reactive PI filter network. However, this will also introduce some chrominance-luminance delay distortion in the range of 10-20 ns for a maximum of 0.5 dB boost at the subcarrier frequency. The filter network feeding an RF modulator may include the aforementioned trap, which could take two forms depending on the depth of attenuation and type of resonator device employed. The trap circuitry can interact with the lowpass filter, compromising frequency response flatness. A simple PNP buffer can preserve the benefits of an oversampling encoder when simultaneous Composite Video Baseband Signals (CVBS) are required for driving external cables. In addition, an active video buffer, serves to isolate the RF modulator signal amplitude from anomalies in the external termination. This buffer can be implemented with a transistor array or video amplify IC which provides a gain of two (before series termination), capable of driving 740 A into the 75 destination, and is biased within its input/output compliance range. When simultaneous Y/C (s-video) outputs are not required, a second CVBS signal can be created (with a 600 mV sync to tip offset) by tying these pins together with a single termination resistor (typically 75 ) and driving the lowpass filter circuit.
3-8
Conexant
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BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
3.0 PC Board Considerations
3.6 BT868/Bt869 Evaluation Board
The RF modulator typically has a high input impedance (about 1k 30%) and loose tolerance. Consequently, the amplitude variation at the modulator input will be greater, especially when the trap is properly terminated at the modulator input for maximum effect. Some modulators, video or aural fidelity, degrade dramatically when overdriven, so the value of the effective termination (nominally 37.5 ) may need to be adjusted downward to maintain sufficient linearity (or depth of modulation margin) in the RF signal. A two-section trap (with associated inductor) may be warranted to achieve better than 20 dB attenuation when stereo, SAP, or AM aural carriers are generated, or when > 40 dB audio dynamic range is desired. Some impedance isolation (e.g., buffer) may be required before the trap to obtain the flattest frequency response. See Figure 3-2.
3.6 BT868/Bt869 Evaluation Board
See Figure 3-4 for a schematic diagram of the BT868 EVK evaluation card. This is a reference design intended to facilitate implementation of Conexant's VGA Encoder into a graphics card. The BT868EVK may be obtained through your local Conexant Semiconductor sales office.
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Conexant
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3.0 PC Board Considerations
3.6 BT868/Bt869 Evaluation Board
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Figure 3-4. BT868/Bt869 Evaluation Board (1 of 6)
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BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Figure 3-4. BT868/Bt869 Evaluation Board (2 of 6)
3.0 PC Board Considerations
3.6 BT868/Bt869 Evaluation Board
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3.0 PC Board Considerations
3.6 BT868/Bt869 Evaluation Board
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Figure 3-4. BT868/Bt869 Evaluation Board (3 of 6)
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BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Figure 3-4. BT868/Bt869 Evaluation Board (4 of 6)
3.0 PC Board Considerations
3.6 BT868/Bt869 Evaluation Board
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3.0 PC Board Considerations
3.6 BT868/Bt869 Evaluation Board
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Figure 3-4. BT868/Bt869 Evaluation Board (5 of 6)
3-14
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BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Figure 3-4. BT868/Bt869 Evaluation Board (6 of 6)
3.0 PC Board Considerations
3.6 BT868/Bt869 Evaluation Board
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Conexant
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3.0 PC Board Considerations
3.7 Serial Interface
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
3.7 Serial Interface
3.7.1 Data Transfer on the Serial Interface Bus
Figure 3-5 illustrates the relationship between SID (Serial Interface Data) and SIC (Serial Interface Clock) to be used when programming the internal registers via the Serial Interface bus. If the bus is not being used, both SID and SIC lines must be left high. Every byte put onto the SID line should be 8 bits long (MSB first), followed by an acknowledge bit, which is generated by the receiving device. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always the slave address byte. If this is the device's own address, the device will generate an acknowledge by pulling the SID line low during the ninth clock pulse, then accept the data in subsequent bytes (auto-incrementing the subaddress) until another stop condition is detected. The eighth bit of the address byte is the read/write bit (high = read from addressed device; low = write to the addressed device) so, for the BT868/869, the subaddress is only considered valid if the R/W bit is low. Data bytes are always acknowledged during the ninth clock pulse by the addressed device. Note that during the acknowledge period, the transmitting device must leave the SID line high. Premature termination of the data transfer is allowed by generating a stop condition at any time. When this happens, the BT868/869 will remain in the state defined by the last complete data byte transmitted and any master acknowledge subsequent to reading the chip ID (subaddress 0x89) is ignored.
Figure 3-5. SID/SIC Diagram
Subsequent Bytes and Acknowledge Interpreted as Data Values for Auto-Incrementing Subaddress Locations
SIC
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
MSB
LSB
SID
Start Condition
(1)
(1)
(1)
Slave Main Address (XX)
Subaddress (XX)
Data (XX)
(1)
Acknowledge generated by BT868/869.
3-16
Conexant
Stop Condition
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4.0 Parametric Information
4.1 DC Electrical Parameters
DC electrical parameters are defined in Tables 4-1 through 4-3. AC electrical parameters are defined in Table 4-4. Timing diagrams are in Figures 4-1 through 4-3.
Table 4-1. Recommended Operating Conditions Parameter
Power Supply Serial Input Supply Ambient Operating Temperature DAC Output Load Nominal RSET
Symbol
VAA, VDD VDD_SI TA RL RSET
Min
3.00 3.00 0
Typ
3.30
Max
3.60 5.25 70
Units
V V C W W
37.5 100.0
Table 4-2. Absolute Maximum Rating (1 of 2) Parameter
VAA, VDD (measured to GND) VDD_SI (measured to GND)
Symbol
Min
Typ
Max
7.0 7.0
Units
V V
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4.0 Parametric Information
4.1 DC Electrical Parameters
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Table 4-2. Absolute Maximum Rating (2 of 2) Parameter
Voltage on Any Signal Pin (1) Analog Output Short Circuit Duration to Any Power Supply or Common Storage Temperature Junction Temperature Vapor Phase Soldering (1 Minute)
(1)
Symbol
Min
GND - 0.5
Typ
Max
VDD_SI+ 0.5
Units
V
ISC TS TJ TVSOL - 65
Indefinite +150 +125 220 C C C
This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply or ground voltage by more than 0.5 V can cause destructive latchup. Stresses above those listed under "Absolute Maximum Ratings" can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability.
Table 4-3. DC Characteristics (1 of 2) Parameter
Video D/A Resolution Output Current-DAC Code 1023 (Iout Full Scale) Output Voltage-DAC Code 1023 Video Level Error (Nominal Resistors) Output Capacitance (of DAC output) Digital Inputs (Except those specified below) Input High Voltage Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f =1 MHz, Vin = 2.4 V) SID, SDO Input High Voltage Input Low Voltage CLKI Input Input High Voltage Input Low Voltage VIH VIL 2.4 GND - 0.5 VDD_I + 0.5 0.8 V V VIH VIL 0.7 * VDD_SI GND - 0.5 VDD_SI + 0.5 0.3 * VDD_SI V V VIH VIL IIH IIL CIN 7 2.0 GND - 0.5 VDD_I + 0.5 0.8 1 -1 V V A A pF 22
Symbol
Min
10
Typ
10 34.13 1.28
Max
10
Units
Bits mA V
5
% pF
4-2
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table 4-3. DC Characteristics (2 of 2) Parameter
Digital Outputs Output High Voltage (IOH = -400 A) Output Low Voltage (IOL = 3.2 mA) Three-State Current Output Capacitance VOH VOL IOZ CDOUT 10 2.4 GND
4.0 Parametric Information
4.1 DC Electrical Parameters
Symbol
Min
Typ
Max
Units
VDD 0.4 50
V V A pF
NOTE(S): Recommended Operating Conditions, NTSC CCIR 601 operation, and internal clock frequency = 27 MHz. As the above
parameters are guaranteed over the full temperature range (0C to 70C), temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 3.3 V.
100123B
Conexant
4-3
4.0 Parametric Information
4.2 AC Electrical Parameters
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
4.2 AC Electrical Parameters
Table 4-4. AC Characteristics (1 of 2) Parameter
Hue Accurac(1, 2) Color Saturation Accuracy(1, 2) Chroma AM/PM Noise(3) Differential Gain(2) Differential Phase(2) SNR (Unweighted 100 IRE Y Ramp Tilt Correct)(2) RMS Peak Periodic 100 IRE Multiburst(3) Gain/frequency Chroma/Luma Gain Ineq(3) Chroma/Luma Delay Ineq(3) Short Time Distortion 100 IRE/PIXEL(3) Luminance Nonlinearity(2) Chroma/Luma Intermod(2) Chroma Nonlinear Gain(2) Chroma Nonlinear Phase(2) Pixel/Control Setup Time(2) Pixel/Control Hold Time(2) Control Output Delay Time(4) Control Output Hold Time(4) CLKI/O Frequency CLKI/O Pulse Width Low Duty Cycle CLKI/O Pulse Width High Duty Cycle 40 40 50 50 6.1.2.2 6.1.2 6.1.6 6.2.1 6.2.3 6.2.4.1 6.2.4.2 1 2 3 4 2 40.5 60 60 3 .35 15 12 6.3.1 6.3.2 6.1.1 C3.5.4.1 C3.5.3.1 C3.5.3.2 dB rms dB p-p 1 MHz Red Field 6.2.2.1 6.2.2.2 C3.4.1.3 C3.4.1.4
EIA/TIA 250C Ref
CCIR 567
Symbol
Min
Typ
Max
Units
x %
dB rms % p-p
x p-p
IRE
IRE
ns % %
IRE IRE x
ns ns ns ns MHz % %
4-4
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table 4-4. AC Characteristics (2 of 2) Parameter
CLKO to CLKI Delay SLAVE to HSYNC*/VSYNC* Three-state SLAVE to HSYNC*/VSYNC* Active VAA Supply Current VAA Power-Down Current VDD Supply Current VDD Power-Down Current Total Supply Current
(1) (2)
4.0 Parametric Information
4.2 AC Electrical Parameters
EIA/TIA 250C Ref
CCIR 567
Symbol
7 5 6
Min
Typ
Max
0.8
Units
CLKO cycles CLKI cycles
2 2 132 1 118 1 250
CLKI cycles mA mA mA mA mA
5/7.5/75/7.5 Color bars normalized to burst. Guaranteed by characterization. (3) Without post filter. Guaranteed by design. (4) Control pins are defined as: P[11:0], BLANK*, HSYNC*, VSYNC*, FIELD, CLKDIR, RESET*, PAL, and SLAVE. 5. "Recommended Operating Conditions," NTSC CCIR 601 operation, and CLK frequency = 27 MHz. Analog output load < 75 pF. HSYNC*, VSYNC*, BLANK*, and FIELD output load < 75 pF. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 3.3 V. Video input and output timing is shown in Figure 4-1.
100123B
Conexant
4-5
4.0 Parametric Information
4.2 AC Electrical Parameters
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Figure 4-1. Interface Timing
CLKO 7
CLKI
P[11:0] 1 HSYNC*,VSYNC*, BLANK* (Input) 1 2 2 1 2
CLKO/CLKI (Internal/External Clock Source) HSYNC*,VSYNC* BLANK* (Output) 4 3 2.4 .8
SLAVE 6 5 HSYNC*,VSYNC*
4-6
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Figure 4-2. Master Mode with Flicker Filter Interface Timing
4.0 Parametric Information
4.2 AC Electrical Parameters
CLKI
P[11:0] (Mux Mode) H_BLANKI - 3 P[23:0] (NonMux Mode) BLANK* (Input) CLKO HSYNC* (Output) Internal Sample Counter VSYNC* (Output) Internal Line Counter BLANK* (Output)
POL POH P1L P1H P2L P2H
PnH
P0
P1
P2
Pn
Sample1 Sample2
Sample1 Sample2
Sample Sample Sample H_Blank H_Blank H_Blank
Sample H_Blank
Line 1
Line V_BLANK1+1
100123B
Conexant
4-7
4.0 Parametric Information
4.2 AC Electrical Parameters
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
Figure 4-3. Slave Mode with Flicker Filter Interface Timing
CLKO
CLKI
POL POH P1L P1H P2L
PnL PnH
H_BLANK P0 P1 P2 Pn
BLANK* (Input) HSYNC* (Input) Internal Sample Counter VSYNC* (Input) BLANK* (Output)
Sample HCLKI Sample H_BLANKI -2 Sample H_BLANKI Sample H_BLANKI -1 Sample H_Blank
Sample1
4-8
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
4.0 Parametric Information
4.3 Mechanical Drawing
4.3 Mechanical Drawing
A detailed mechanical diagram is shown in Figure 0-1.
Figure 0-1. 80 MQFP Package Diagram
80 MQFP - 1.6/0.15mm FORM
TOP VIEW
D D2
BOTTOM VIEW
D1
E2 e b
E
E1
SIDE VIEW
A
S Y M B O L
ALL DIMENSIONS IN MILLIMETERS
DETAIL A
A A1 A2 D
MIN. --0.05 16.95
NOM. ----2.0 REF. --14.0 REF. 12.35 REF.
MAX. 2.4 0.35 17.45
A2
D1 D2 E E1 E2 L L1 e b 0.25 0.73 16.95
--14.0 REF. 12.35 REF. 0.80 16 REF. 0.65 BSC ---
17.45
A1
L
1.60 (.063) REF.
1.03
0.45
100123B
Conexant
4-9
4.0 Parametric Information
4.3 Mechanical Drawing
BT868/Bt869 Flicker-Free Video Encoder with Ultrascale
TM
Technology
4-10
Conexant
100123B
A
Appendix A. Scaling and I/O Timing Register Calculations
The calculated values are used to program the registers controlling the total active pixels and lines in the input frame and the output field, as well as the vertical scaling register and the clock PLL registers. These calculations assume pixel resolution for synchronizing the graphics controller, and master mode operation unless otherwise stated, and require the following input values: MFP--Minimum Front Porch Blanking in the Input in Clocks = max (12, Controller_Minimum_Front_Porch_Blanking_Clocks); MBP--Minimum Back Porch Blanking in the Input in Clocks = max (4, Controller_Minimum_Back_Porch_Blanking_Clocks); VOC--desired Vertical Overscan Compensation (e.g., 0.15) HOC--desired Horizontal Overscan Compensation (e.g., 0.15) V_ACTIVEI--Active Lines per Input Frame (e.g., 480 or 600) H_ACTIVE--Active Pixels per Input Line (e.g., 640 or 800) ALO--Target Active Lines per Output Field (See Table A-2) TLO--Total Lines per Output Field (See Table A-2) ATO--Active Time per Output Line (See Table A-2) TTO--Total Time per Output Line (See Table A-2) Table A-1 displays details of the video formats. Table A-2 details the constant values dependent on encoding modes. Figures A-1 through A-4 diagram overscan compensation. Tables A-3 through A-10 display overscan values.
Table A-1. Video Formats Mode
FSC (Hz) Burst Start Burst End HSYNC Width HSYNC Frequency Active Begin Image Center Front Porch
NTSC
NTSC60Hz
PALBDGHI
PAL-N
PAL-Nc
PAL-M
PAL-M60Hz
PAL-60
3,579,545 3,579,545 4,433,618.75 4,433,618.75 3,582,056.25 3,575,611.88 3,575,611.88 4,433,619.49 5.3 s 7.82 s 4.70 s 63.555 s 9.40 s 5.3 s 7.82s 4.70 s 64 s 9.40 s 5.60 s 7.85 s 4.70 s 64 s 10.5 s 36.407 s 1.50 s 5.60 s 7.85 s 4.70 s 64 s 9.40 s 35.667 s 1.50 s 5.60 s 8.11 s 4.70 s 64 s 10.5 s 36.407 s 1.50 s 5.80 s 8.32 s 4.70 s 63.555 s 9.40 s 35.667 s 1.50 s 5.80 s 8.32 s 4.70 s 64 s 9.40 s 35.667 s 1.50 s 5.60 s 7.85 s 4.70 s 64 s 10.5 s 36.407 s 1.50 s
35.667 s 35.667 s 1.50 s 1.50 s
100123B
Conexant
A-1
Appendix A . Scaling and I/O Timing Register Calculations
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table A-2. Constant Values Dependent on Encoding Mode Modes
PAL ALO TLO ATO TTO 288 312.5 52.0 s 64.0 s
Interlaced
NTSC 243 262.5 52.65556 s 63.55556 s PAL 288 312
Non-Interlaced
NTSC 243 262 52.65556 s 63.55556 s
52.0 s 64.0 s
Figure A-1. Overscan Compensation, 640x480 NTSC, 20 Clock Hblank
Overscan Compensation Pecentage Pairs for 640x480 NTSC w/ Character Clock 1 +, 8 *, 9 o 22
20
18
Horizontal Overscan Compensation Percentage
16
14
12
10
8 8 10 12 14 16 18 20 22 Vertical Overscan Compensation Percentage
A-2
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Appendix A . Scaling and I/O Timing Register Calculations
Figure A-2. Overscan Compensation, 640x480 PAL, 20 Clock Hblank
Overscan Compensation Pecentage Pairs for 640x480 PAL w/ Character Clock 1 +, 8 *, 9 o 24
22
20
Horizontal Overscan Compensation Percentage
18
16
14
12
10
8 8 10 12 14 16 18 20 22 Vertical Overscan Compensation Percentage
100123B
Conexant
A-3
Appendix A . Scaling and I/O Timing Register Calculations
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Figure A-3. Overscan Compensation, 800x600 NTSC
Overscan Compensation Percentage Pairs for 800x600 NTSC w/ Character Clock 1 +, 8 *, 9 o 24
22
3 us
20
2 us Horizontal Overscan Compensation Percentage 18
16
1 us 14 .75 us
12
0 us Horizontal Blanking 10
8 8 10 12 14 16 18 20 22 Vertical Overscan Compensation Percentage
A-4
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Figure A-4. Overscan Compensation, 800x600 PAL
Appendix A . Scaling and I/O Timing Register Calculations
Overscan Compensation Pecentage Pairs for 800x600 PAL w/ Character Clock 1 +, 8 *, 9 o 22
20
18
Horizontal Overscan Compensation Percentage
16
14
12
10
8 8 10 12 14 16 18 20 22 Vertical Overscan Compensation Percentage
Table A-3. Overscan Values, 640x480 NTSC, 1 Pixel Resolution, 2.5 Ps Hblank (1 of 3) Controller Pixels Total H_CLKI
780 780 784 780 777 785 777 777 775 775
Encoder Pixels Overscan (Percent) Active Total H_CLKO
988 884 896 936 851 942 925 962 868 961
V_LINESI
665 595 600 630 575 630 625 650 588 651
V_ACTIVEO
190 212 210 200 220 200 202 194 215 194
H
21.81 12.61 13.79 17.47 9.23 18.00 16.49 19.70 11.00 19.62
V
21.81 12.76 13.58 17.70 9.47 17.70 16.87 20.16 11.52 20.16
Delta
0.00 -0.14 0.21 -0.23 -0.24 0.30 -0.38 -0.46 -0.52 -0.55
100123B
Conexant
A-5
Appendix A . Scaling and I/O Timing Register Calculations
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table A-3. Overscan Values, 640x480 NTSC, 1 Pixel Resolution, 2.5 Ps Hblank (2 of 3) Controller Pixels Total H_CLKI
777 775 775 790 791 770 770 770 770 770 795 770 795 765 798 798 798 800 765 765 800 798 763 800 805 760 805 805 805 756
Encoder Pixels Overscan (Percent) Active Total H_CLKO
888 899 930 948 904 946 858 968 902 924 954 880 901 969 988 912 950 960 918 867 928 874 872 896 966 912 943 920 989 936
V_LINESI
600 609 630 630 600 645 585 660 615 630 630 600 595 665 650 600 625 630 630 595 609 575 600 588 630 630 615 600 645 650
V_ACTIVEO
210 207 200 200 210 196 216 191 205 200 200 210 212 190 194 210 202 200 200 212 207 220 210 215 200 200 205 210 196 194
H
13.01 14.07 16.94 18.51 14.55 18.34 9.97 20.20 14.36 16.40 19.03 12.22 14.26 20.28 21.81 15.30 18.69 19.53 15.85 10.90 16.76 11.62 11.41 13.79 20.03 15.30 18.08 16.03 21.89 17.47
V
13.58 14.81 17.70 17.70 13.58 19.34 11.11 21.40 15.64 17.70 17.70 13.58 12.76 21.81 20.16 13.58 16.87 17.70 17.70 12.76 14.81 9.47 13.58 11.52 17.70 17.70 15.64 13.58 19.34 20.16
Delta
-0.57 -0.74 -0.76 0.82 0.97 -1.00 -1.14 -1.20 -1.28 -1.30 1.33 -1.36 1.51 -1.53 1.65 1.72 1.81 1.84 -1.84 -1.86 1.94 2.15 -2.17 2.26 2.34 -2.40 2.44 2.45 2.55 -2.69
A-6
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Appendix A . Scaling and I/O Timing Register Calculations
Table A-3. Overscan Values, 640x480 NTSC, 1 Pixel Resolution, 2.5 Ps Hblank (3 of 3) Controller Pixels Total H_CLKI
756 805 810 755 805 756
Encoder Pixels Overscan (Percent) Active Total H_CLKO
900 897 972 906 874 864
V_LINESI
625 585 630 630 570 600
V_ACTIVEO
202 216 200 200 222 210
H
14.17 13.88 20.53 14.74 11.62 10.59
V
16.87 11.11 17.70 17.70 8.64 13.58
Delta
-2.70 2.77 2.83 -2.96 2.97 -2.99
Table A-4. Overscan Values, 640x480 NTSC, 8 Pixel Resolution, 2.5 Ps Hblank Controller Pixels Total H_CLKI
784 800 800 800 760 840 840 840 840 840 840 840 840 720 840 840 720
Encoder Pixels Overscan (Percent) Active Total H_CLKO
896 960 928 896 912 984 960 976 952 968 944 936 928 912 920 912 864
V_LINESI
600 630 609 588 630 615 600 610 595 605 590 585 580 665 575 570 630
V_ACTIVEO
210 200 207 215 200 205 210 207 212 209 214 216 218 190 220 222 200
H
13.79 19.53 16.76 13.79 15.30 21.50 19.53 20.85 18.86 20.20 18.17 17.47 16.76 15.30 16.03 15.30 10.59
V
13.58 17.70 14.81 11.52 17.70 15.64 13.58 14.81 12.76 13.99 11.93 11.11 10.29 21.81 9.47 8.64 17.70
Delta
0.21 1.84 1.94 2.26 -2.40 5.86 5.95 6.04 6.10 6.21 6.23 6.36 6.47 -6.51 6.57 6.66 -7.10
100123B
Conexant
A-7
Appendix A . Scaling and I/O Timing Register Calculations
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table A-5. Overscan Values, 640x480 NTSC, 9 Pixel Resolution, 2.5 Ps Hblank Controller Pixels Total H
765 765 765 756 756 810 756 810 819 819 819 720 720 855 693 882 900 675
Encoder Pixels Overscan (Percent) Active Total H
969 918 867 936 900 972 864 918 936 975 897 912 864 969 858 966 984 855
V
665 630 595 650 625 630 600 595 600 625 575 665 630 595 650 575 574 665
V
190 200 212 194 202 200 210 212 210 202 220 190 200 212 194 220 220 190
H
20.28 15.85 10.90 17.47 14.17 20.53 10.59 15.85 17.47 20.77 13.88 15.30 10.59 20.28 9.97 20.03 21.50 9.65
V
21.81 17.70 12.76 20.16 16.87 17.70 13.58 12.76 13.58 16.87 9.47 21.81 17.70 12.76 20.16 9.47 9.47 21.81
Delta
-1.53 -1.84 -1.86 -2.69 -2.70 2.83 -2.99 3.09 3.89 3.90 4.42 -6.51 -7.10 7.52 -10.20 10.57 12.03 -12.16
Table A-6. Overscan Values, 640x480 PAL, 1 Pixel Resolution, 2.5 Ps Hblank (1 of 4) Controller Pixels Total H
945 946 944 947 943 948 942 949
Encoder Pixels Overscan (Percent) Active Total H
945 946 944 947 943 948 942 949
V
625 625 625 625 625 625 625 625
V
240 240 240 240 240 240 240 240
H
16.65 16.73 16.56 16.82 16.47 16.91 16.38 17.00
V
16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67
Delta
-0.02 0.07 -0.11 0.16 -0.20 0.24 -0.29 0.33
A-8
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Appendix A . Scaling and I/O Timing Register Calculations
Table A-6. Overscan Values, 640x480 PAL, 1 Pixel Resolution, 2.5 Ps Hblank (2 of 4) Controller Pixels Total H
941 950 950 940 950 950 951 939 952 938 953 937 954 936 955 935 956 934 957 933 958 932 959 931 960 930 961 962 929 963 928 964
Encoder Pixels Overscan (Percent) Active Total H
941 950 912 940 988 874 951 939 952 938 953 937 954 936 955 935 956 934 957 933 958 932 959 931 960 930 961 962 929 963 928 964
V
625 625 600 625 650 575 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625
V
240 240 250 240 231 261 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
H
16.29 17.09 13.63 16.20 20.27 9.88 17.17 16.11 17.26 16.02 17.35 15.93 17.43 15.84 17.52 15.75 17.61 15.66 17.69 15.57 17.78 15.48 17.86 15.39 17.95 15.30 18.03 18.12 15.21 18.20 15.12 18.29
V
16.67 16.67 13.19 16.67 19.79 9.38 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67
Delta
-0.37 0.42 0.44 -0.46 0.48 0.50 0.51 -0.55 0.59 -0.64 0.68 -0.73 0.77 -0.82 0.85 -0.91 0.94 -1.00 1.02 -1.09 1.11 -1.18 1.20 -1.27 1.28 -1.36 1.37 1.45 -1.46 1.54 -1.55 1.62
100123B
Conexant
A-9
Appendix A . Scaling and I/O Timing Register Calculations
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table A-6. Overscan Values, 640x480 PAL, 1 Pixel Resolution, 2.5 Ps Hblank (3 of 4) Controller Pixels Total H
927 925 965 926 966 925 967 925 924 968 923 969 922 970 921 971 920 972 973 919 974 918 975 917 976 975 916 977 915
Encoder Pixels Overscan (Percent) Active Total H
927 962 965 926 966 925 967 888 924 968 923 969 922 970 921 971 920 972 973 919 974 918 975 917 976 936 916 977 915
V
625 650 625 625 625 625 625 600 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 600 625 625 625
V
240 231 240 240 240 240 240 250 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 250 240 240 240
H
15.03 18.12 18.37 14.94 18.46 14.84 18.54 11.30 14.75 18.63 14.66 18.71 14.57 18.79 14.47 18.88 14.38 18.96 19.04 14.29 19.13 14.19 19.21 14.10 19.29 15.84 14.01 19.38 13.91
V
16.67 19.79 16.67 16.67 16.67 16.67 16.67 13.19 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 13.19 16.67 16.67 16.67
Delta
-1.64 -1.67 1.71 -1.73 1.79 -1.82 1.88 -1.90 -1.91 1.96 -2.01 2.04 -2.10 2.13 -2.19 2.21 -2.29 2.30 2.38 -2.38 2.46 -2.47 2.54 -2.57 2.63 2.65 -2.66 2.71 -2.75
A-10
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Appendix A . Scaling and I/O Timing Register Calculations
Table A-6. Overscan Values, 640x480 PAL, 1 Pixel Resolution, 2.5 Ps Hblank (4 of 4) Controller Pixels Total H
978 975 914 979 913 980
Encoder Pixels Overscan (Percent) Active Total H
978 897 914 979 913 980
V
625 575 625 625 625 625
V
240 261 240 240 240 240
H
19.46 12.19 13.82 19.54 13.72 19.62
V
16.67 9.38 16.67 16.67 16.67 16.67
Delta
2.79 2.81 -2.85 2.87 -2.94 2.96
Table A-7. Overscan Values, 640x480 PAL, 8 Pixel Resolution, 2.5 Ps Hblank (1 of 2) Controller Pixels Total H
944 952 936 960 928 968 920 976 912 984 904 992 1000 896 1000 1000 1000 1000 1000 1000 1000
Encoder Pixels Overscan (Percent) Active Total H
944 952 936 960 928 968 920 976 912 984 904 992 1000 896 992 984 976 968 960 1008 920
V
625 625 625 625 625 625 625 625 625 625 625 625 625 625 620 615 610 605 600 630 575
V
240 240 240 240 240 240 240 240 240 240 240 240 240 240 242 244 246 248 250 239 261
H
16.56 17.26 15.84 17.95 15.12 18.63 14.38 19.29 13.63 19.95 12.87 20.60 21.23 12.09 20.60 19.95 19.29 18.63 17.95 21.86 14.38
V
16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 15.97 15.28 14.58 13.89 13.19 17.01 9.38
Delta
-0.11 0.59 -0.82 1.28 -1.55 1.96 -2.29 2.63 -3.04 3.28 -3.80 3.93 4.56 -4.58 4.62 4.67 4.71 4.74 4.75 4.84 5.01
100123B
Conexant
A-11
Appendix A . Scaling and I/O Timing Register Calculations
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table A-7. Overscan Values, 640x480 PAL, 8 Pixel Resolution, 2.5 Ps Hblank (2 of 2) Controller Pixels Total H
1000 1000 1000 1000 1008 888 880 872
Encoder Pixels Overscan (Percent) Active Total H
928 936 944 952 1008 888 880 872
V
580 585 590 595 625 625 625 625
V
259 257 255 253 240 240 240 240
H
15.12 15.84 16.56 17.26 21.86 11.30 10.49 9.67
V
10.07 10.76 11.46 12.15 16.67 16.67 16.67 16.67
Delta
5.05 5.08 5.10 5.11 5.19 -5.37 -6.18 -7.00
Table A-8. Overscan Values, 640x480 PAL, 9 Pixel Resolution, 2.5 Ps Hblank Controller Pixels Total H
945 954 936 963 927 972 918 981 909 990 900 900 999 891 1008 882 873
Encoder Pixels Overscan (Percent) Active Total H
945 954 936 963 927 972 918 981 909 990 936 900 999 891 1008 882 873
V
625 625 625 625 625 625 625 625 625 625 650 625 625 625 625 625 625
V
240 240 240 240 240 240 240 240 240 240 231 240 240 240 240 240 240
H
16.65 17.43 15.84 18.20 15.03 18.96 14.19 19.71 13.35 20.44 15.84 12.48 21.15 11.59 21.86 10.69 9.77
V
16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 19.79 16.67 16.67 16.67 16.67 16.67 16.67
Delta
-0.02 0.77 -0.82 1.54 -1.64 2.30 -2.47 3.04 -3.32 3.77 -3.95 -4.19 4.49 -5.07 5.19 -5.97 -6.89
A-12
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table A-9. Overscan Values, 800x600 NTSC (1 of 5) Controller Pixels Total H
800 800 800 800 800 800 805 805 805 805 805 805 805 805 810 810 812 810 819 815 819 819 825 819 825 820 825 825 825 826 825 825
Appendix A . Scaling and I/O Timing Register Calculations
Encoder Pixels Overscan (Percent) Active Total H
1184 1248 1216 1152 1088 1120 1265 1196 1150 1173 1242 1104 1219 1127 1242 1188 1160 1134 1248 1141 1170 1209 1265 1131 1232 1148 1221 1254 1210 1180 1243 1199
Hblank and Character Clock Resolution Delta
1.98 2.05 2.07 2.19 2.20 2.26 2.27 2.39 2.45 2.45 2.50 2.66 2.68 2.80 2.91 3.08 3.18 3.33 3.70 3.85 3.89 4.08 4.33 4.34 4.34 4.37 4.46 4.48 4.56 4.59 4.62 4.65
V
777 819 798 756 714 735 825 780 750 765 810 720 795 735 805 770 750 735 800 735 750 775 805 725 784 735 777 798 770 750 791 763
V
203 193 198 209 221 215 191 202 210 206 195 219 199 215 196 205 210 215 197 215 210 204 196 218 201 215 203 198 205 210 200 207
H
18.45 22.63 20.59 16.18 11.25 13.79 23.67 19.26 16.03 17.68 22.25 12.54 20.79 14.32 22.25 18.72 16.76 14.85 22.63 15.37 17.47 20.13 23.67 14.62 21.62 15.89 20.92 23.00 20.20 18.17 22.32 19.47
V
16.46 20.58 18.52 13.99 9.05 11.52 21.40 16.87 13.58 15.23 19.75 9.88 18.11 11.52 19.34 15.64 13.58 11.52 18.93 11.52 13.58 16.05 19.34 10.29 17.28 11.52 16.46 18.52 15.64 13.58 17.70 14.81
Hblank
0.00 0.00 0.00 0.00 0.00 0.00 0.13 0.13 0.14 0.14 0.13 0.14 0.13 0.14 0.26 0.27 0.33 0.28 0.48 0.42 0.52 0.50 0.63 0.53 0.64 0.55 0.65 0.63 0.66 0.70 0.64 0.66
Resol
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
100123B
Conexant
A-13
Appendix A . Scaling and I/O Timing Register Calculations
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table A-9. Overscan Values, 800x600 NTSC (2 of 5) Controller Pixels Total H
825 825 825 825 825 825 825 833 830 840 840 835 840 840 840 840 840 840 840 840 840 840 840 840 840 840 847 850 845 850 854 850
Encoder Pixels Overscan (Percent) Active Total H
1188 1177 1166 1155 1122 1144 1133 1190 1162 1248 1256 1169 1224 1264 1200 1232 1208 1240 1184 1216 1168 1192 1152 1176 1160 1144 1210 1258 1183 1224 1220 1190
Hblank and Character Clock Resolution Delta
4.73 4.79 4.84 4.88 4.89 4.89 4.90 5.28 5.38 5.76 5.84 5.88 5.88 5.91 5.95 5.99 6.07 6.08 6.10 6.19 6.22 6.24 6.30 6.37 6.47 6.54 6.62 6.78 6.85 7.12 7.27 7.33
V
756 749 742 735 714 728 721 750 735 780 785 735 765 790 750 770 755 775 740 760 730 745 720 735 725 715 750 777 735 756 750 735
V
209 211 213 215 221 217 219 210 215 202 201 215 206 200 210 205 209 204 213 208 216 212 219 215 218 221 210 203 215 209 210 215
H
18.72 17.96 17.19 16.40 13.94 15.59 14.77 18.86 16.90 22.63 23.12 17.40 21.11 23.61 19.53 21.62 20.07 22.13 18.45 20.59 17.33 18.99 16.18 17.89 16.76 15.59 20.20 23.24 18.38 21.11 20.85 18.86
V
13.99 13.17 12.35 11.52 9.05 10.70 9.88 13.58 11.52 16.87 17.28 11.52 15.23 17.70 13.58 15.64 13.99 16.05 12.35 14.40 11.11 12.76 9.88 11.52 10.29 9.05 13.58 16.46 11.52 13.99 13.58 11.52
Hblank
0.67 0.67 0.68 0.69 0.71 0.69 0.70 0.88 0.82 1.02 1.01 0.95 1.04 1.01 1.06 1.03 1.05 1.03 1.07 1.05 1.09 1.07 1.10 1.08 1.10 1.11 1.23 1.26 1.21 1.30 1.41 1.34
Resol
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A-14
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table A-9. Overscan Values, 800x600 NTSC (3 of 5) Controller Pixels Total H
855 850 855 861 861 860 861 868 865 875 875 870 875 875 875 875 875 875 875 875 875 875 875 875 875 882 875 875 880 889 882 885
Appendix A . Scaling and I/O Timing Register Calculations
Encoder Pixels Overscan (Percent) Active Total H
1254 1156 1197 1230 1271 1204 1189 1240 1211 1270 1250 1218 1265 1245 1240 1260 1235 1255 1210 1230 1205 1225 1200 1195 1220 1260 1190 1215 1232 1270 1218 1239
Hblank and Character Clock Resolution Delta
7.36 7.42 7.81 7.92 7.98 8.28 8.50 8.55 8.74 9.15 9.17 9.20 9.26 9.27 9.37 9.37 9.47 9.48 9.50 9.56 9.58 9.65 9.66 9.73 9.74 9.78 9.80 9.83 10.10 10.39 10.43 10.54
V
770 714 735 750 775 735 725 750 735 762 750 735 759 747 744 756 741 753 726 738 723 735 720 717 732 750 714 729 735 750 725 735
V
205 221 215 210 204 215 218 210 215 207 210 215 208 211 212 209 213 210 217 214 218 215 219 220 216 210 221 217 215 210 218 215
H
23.00 16.47 19.33 21.50 24.03 19.80 18.79 22.13 20.26 23.97 22.75 20.72 23.67 22.44 22.13 23.36 21.81 23.06 20.20 21.50 19.87 21.18 19.53 19.20 20.85 23.36 18.86 20.53 21.62 23.97 20.72 22.07
V
15.64 9.05 11.52 13.58 16.05 11.52 10.29 13.58 11.52 14.81 13.58 11.52 14.40 13.17 12.76 13.99 12.35 13.58 10.70 11.93 10.29 11.52 9.88 9.47 11.11 13.58 9.05 10.70 11.52 13.58 10.29 11.52
Hblank
1.39 1.37 1.46 1.58 1.53 1.58 1.63 1.74 1.71 1.88 1.91 1.83 1.88 1.91 1.92 1.89 1.93 1.90 1.97 1.94 1.98 1.95 1.99 1.99 1.95 2.07 2.00 1.96 2.06 2.23 2.14 2.18
Resol
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
100123B
Conexant
A-15
Appendix A . Scaling and I/O Timing Register Calculations
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table A-9. Overscan Values, 800x600 NTSC (4 of 5) Controller Pixels Total H
890 895 900 900 900 900 905 903 910 925 800 800 800 800 800 800 840 840 840 840 840 840 840 840 840 840 840 840 840 840 840 840
Encoder Pixels Overscan (Percent) Active Total H
1246 1253 1260 1248 1236 1224 1267 1247 1248 1258 1184 1248 1216 1152 1088 1120 1248 1256 1224 1264 1200 1232 1208 1240 1184 1216 1168 1192 1152 1176 1160 1144
Hblank and Character Clock Resolution Delta
10.98 11.41 11.84 11.93 12.00 12.06 12.27 12.28 12.75 14.19 1.98 2.05 2.07 2.19 2.20 2.26 5.76 5.84 5.88 5.91 5.95 5.99 6.07 6.08 6.10 6.19 6.22 6.24 6.30 6.37 6.47 6.54
V
735 735 735 728 721 714 735 725 720 714 777 819 798 756 714 735 780 785 765 790 750 770 755 775 740 760 730 745 720 735 725 715
V
215 215 215 217 219 221 215 218 219 221 203 193 198 209 221 215 202 201 206 200 210 205 209 204 213 208 216 212 219 215 218 221
H
22.50 22.94 23.36 22.63 21.88 21.11 23.79 22.57 22.63 23.24 18.45 22.63 20.59 16.18 11.25 13.79 22.63 23.12 21.11 23.61 19.53 21.62 20.07 22.13 18.45 20.59 17.33 18.99 16.18 17.89 16.76 15.59
V
11.52 11.52 11.52 10.70 9.88 9.05 11.52 10.29 9.88 9.05 16.46 20.58 18.52 13.99 9.05 11.52 16.87 17.28 15.23 17.70 13.58 15.64 13.99 16.05 12.35 14.40 11.11 12.76 9.88 11.52 10.29 9.05
Hblank
2.30 2.41 2.52 2.55 2.57 2.60 2.63 2.62 2.80 3.16 0.00 0.00 0.00 0.00 0.00 0.00 1.02 1.01 1.04 1.01 1.06 1.03 1.05 1.03 1.07 1.05 1.09 1.07 1.10 1.08 1.10 1.11
Resol
1 1 1 1 1 1 1 1 1 1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
A-16
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table A-9. Overscan Values, 800x600 NTSC (5 of 5) Controller Pixels Total H
880 810 810 810 819 819 819 819 855 855 882 882 900 900 900 900
Appendix A . Scaling and I/O Timing Register Calculations
Encoder Pixels Overscan (Percent) Active Total H
1232 1242 1188 1134 1248 1170 1209 1131 1254 1197 1260 1218 1260 1248 1236 1224
Hblank and Character Clock Resolution Delta
10.10 2.91 3.08 3.33 3.70 3.89 4.08 4.34 7.36 7.81 9.78 10.43 11.84 11.93 12.00 12.06
V
735 805 770 735 800 750 775 725 770 735 750 725 735 728 721 714
V
215 196 205 215 197 210 204 218 205 215 210 218 215 217 219 221
H
21.62 22.25 18.72 14.85 22.63 17.47 20.13 14.62 23.00 19.33 23.36 20.72 23.36 22.63 21.88 21.11
V
11.52 19.34 15.64 11.52 18.93 13.58 16.05 10.29 15.64 11.52 13.58 10.29 11.52 10.70 9.88 9.05
Hblank
2.06 0.26 0.27 0.28 0.48 0.52 0.50 0.53 1.39 1.46 2.07 2.14 2.52 2.55 2.57 2.60
Resol
8 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9
Table A-10. Overscan Values, 800x600, PAL, > 2.5 Ps Hblank (1 of 3) Controller Pixels Total H
945 950 950 940 950 950 950 955 935 960 930
Encoder Pixels Overscan (Percent) Active Total H
1134 1140 1178 1128 1102 1216 1254 1146 1122 1152 1116
Character Clock Delta
-0.02 0.44 0.44 -0.48 0.58 0.63 0.65 0.89 -0.95 1.34 -1.42
V
750 750 775 750 725 800 825 750 750 750 750
V
250 250 242 250 259 235 228 250 250 250 250
H
13.17 13.63 16.42 12.71 10.65 19.03 21.48 14.08 12.24 14.53 11.77
V
13.19 13.19 15.97 13.19 10.07 18.40 20.83 13.19 13.19 13.19 13.19
Resol
1 1 1 1 1 1 1 1 1 1 1
100123B
Conexant
A-17
Appendix A . Scaling and I/O Timing Register Calculations
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Table A-10. Overscan Values, 800x600, PAL, > 2.5 Ps Hblank (2 of 3) Controller Pixels Total H
925 925 965 925 925 970 920 975 975 975 915 975 980 910 985 900 905 900 990 900 995 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 960
Encoder Pixels Overscan (Percent) Active Total H
1221 1184 1158 1147 1110 1164 1104 1209 1170 1248 1098 1131 1176 1092 1182 1188 1086 1152 1188 1116 1194 1256 1240 1200 1248 1216 1232 1192 1168 1208 1224 1152
Character Clock Delta
-1.47 -1.56 1.78 -1.81 -1.90 2.22 -2.38 2.59 2.65 2.70 -2.87 2.87 3.08 -3.36 3.50 -3.71 -3.86 -3.87 3.93 -4.20 4.34 4.59 4.62 4.75 4.79 4.79 4.80 4.90 4.94 4.95 4.97 1.34
V
825 800 750 775 750 750 750 775 750 800 750 725 750 750 750 825 750 800 750 775 750 785 775 750 780 760 770 745 730 755 765 750
V
228 235 250 242 250 250 250 242 250 235 250 259 250 250 250 228 250 235 250 242 250 239 242 250 241 247 244 252 257 249 246 250
H
19.36 16.84 14.97 14.16 11.30 15.41 10.81 18.56 15.84 21.10 10.33 12.94 16.27 9.83 16.70 17.12 9.34 14.53 17.12 11.77 17.54 21.61 20.60 17.95 21.10 19.03 20.08 17.40 15.70 18.49 19.56 14.53
V
20.83 18.40 13.19 15.97 13.19 13.19 13.19 15.97 13.19 18.40 13.19 10.07 13.19 13.19 13.19 20.83 13.19 18.40 13.19 15.97 13.19 17.01 15.97 13.19 16.32 14.24 15.28 12.50 10.76 13.54 14.58 13.19
Resol
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8
A-18
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Appendix A . Scaling and I/O Timing Register Calculations
Table A-10. Overscan Values, 800x600, PAL, > 2.5 Ps Hblank (3 of 3) Controller Pixels Total H
920 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1040 945 900 900 990 900 1035
Encoder Pixels Overscan (Percent) Active Total H
1104 1256 1240 1200 1248 1216 1232 1192 1168 1208 1224 1184 1160 1152 1176 1144 1248 1134 1188 1152 1188 1116 1242
Character Clock Delta
-2.38 4.59 4.62 4.75 4.79 4.79 4.80 4.90 4.94 4.95 4.97 5.03 5.05 5.15 5.16 5.25 7.91 -0.02 -3.71 -3.87 3.93 -4.20 7.53
V
750 785 775 750 780 760 770 745 730 755 765 740 725 720 735 715 750 750 825 800 750 775 750
V
250 239 242 250 241 247 244 252 257 249 246 254 259 261 256 263 250 250 228 235 250 242 250
H
10.81 21.61 20.60 17.95 21.10 19.03 20.08 17.40 15.70 18.49 19.56 16.84 15.12 14.53 16.27 13.93 21.10 13.17 17.12 14.53 17.12 11.77 20.72
V
13.19 17.01 15.97 13.19 16.32 14.24 15.28 12.50 10.76 13.54 14.58 11.81 10.07 9.38 11.11 8.68 13.19 13.19 20.83 18.40 13.19 15.97 13.19
Resol
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9
100123B
Conexant
A-19
Appendix A . Scaling and I/O Timing Register Calculations
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
A-20
Conexant
100123B
B
Appendix B. Approved Crystal Vendors
Conexant conducted a series of internal tests and used the results to generate this list of approved crystal vendors. Contact your local Conexant Field Applications Engineer for additional details.
Standard Crystal (El Monte, CA)
Phone Number: (626)443-2121 FAX Number: (626)443-9049 E-mail: stdxtl@worldnet.att.net Part Numbers for 13.500 MHz, Fundamental, 20pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: AAK13M500000GXE20A Half-Height/50 ppm: AAL13M500000GXE20A Full Height/25 ppm: Did Not Qualify
MMD Components (Irvine, CA)
Phone Number: (949)753-5888 FAX Number: (949)753-5889 E-mail: mmdcomp@earthlink.net Part Numbers for 13.500 MHz, Fundamental, 20pF Load Crystal with an HC49U Type of Package: Full Height/50ppm Total Tolerance: A20BA1-13.500 MHz. Half-Height/50 ppm: B20BA1-13,500 MHz Full Height/25 ppm: Did Not Qualify
General Electronics (San Marcos, CA)
Phone Number: (760)591-4170 FAX Number: (760)591-4164 E-mail: gedlm@4dcomm.com Part Numbers for 13.500 MHz, Fundamental, 20pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: PKHC49/U-13.500-.020-.005 Half-Height/50 ppm: PKHC49/US-13.500-.020-.005 Full Height/25 ppm: PKHC49/U-13.500-.0025-15R
Fox Electronics (Fort Myers, FL)
Phone Number: (941)693-0099 FAX Number: (941)693-1554 E-mail: barbc@foxonline.com Part Numbers for 13.500 MHz, Fundamental, 20pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: HC49U-13.500 MHz-/50/0/70/20 pF Half Height/50 ppm: HC49S 13.500-/50/0/70/20 pF Full Height/25 ppm: HC49U 13.500-/25/0/70/20 pF
100123B
Conexant
B-1
Appendix B . Approved Crystal Vendors
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Bomar (Middlesex, NJ)
Phone Number: (732)356-7787 FAX Number: (732)356-7362 E-mail: sales@bomarcrystal.com Part Numbers for 13.500 MHz, Fundamental, 20pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: BRC1C14F-13.50000 Half Height/50 ppm: ACR-49S012025-13.50000 Full Height/25 ppm: BRCIE14F-13.50000
HY-Q (Erlanger, Kentucky)
Phone Number: (606)283-5000 FAX Number: (606)283-0883 E-mail: Cpainter@hyqusa.com Part Numbers for 13.500 MHz, Fundamental, 20pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: HT81818/01 Half Height/50 ppm: SC30002/01 HT81819/01 Full Height/25 ppm:
ILSI America (Kirkland, WA)
Phone Number: (425)828-4886 / (888)355-4574 FAX Number: (425)828-4878 E-mail: ilsiam@ilsiamerica.co Part Numbers for 13.500 MHz, Fundamental, 20pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: HC49U-25/25-13.500-20 Half Height/50 ppm: HC49US-FB1F20-13.500 Full Height/25 ppm: Did Not Qualify
Cardinal Components (Wayne, NJ)
Phone Number: (973)785-1333 FAX Number: (973)785-0053 E-mail: dbabcock@cardinalxtal.com Part Numbers for 13.500 MHz, Fundamental, 20pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: C49-A4BRC7-25-13.5D20 Half Height/50 ppm: CLP-A4B6C4-50-13.5D20 Full Height/25 ppm: C49-A4B6C4-25-13.5D20
Raltron Electronics Corp. (Miami, FL)
Phone Number: (305)593-6033 FAX Number: (305)594-3973 E-mail: maria@raltron.com Part Numbers for 13.500 MHz, Fundamental, 20pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: A-13.500-20-RS1 Half Height/50 ppm: AS-13.500-20-RS1 Full Height/25 ppm: A-13.500-20-RS1
Valpey-Fisher (Hopkinton, MA)
Phone Number: FAX Number: (800)982-5737 (508)497-6377
B-2
Conexant
100123B
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
Appendix B . Approved Crystal Vendors
E-mail: angleassoc@aol.com Part Numbers for 13.500 MHz, Fundamental, 20pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: M490013.500020RSVM Half Height/50 ppm: M49K013.50002099VM Full Height/25 ppm: M490013.50002099VM
Telequarz Group (Germany)
Phone Number: Telequarz-USA Inc. (Ft. Mill, SC): (803)547-0770 FAX Number: (507)547-0775 E-mail: info@telequarz.de Part Numbers for 13.500 MHz, Fundamental, 20pF Load Crystal with an HC49U Type of Package: TQ RSD 13.5FH50 Full Height/50 ppm Total Tolerance: TQRSD 13.5LP50 Half Height/50 ppm: TQ RSD 13.5FH25 Full Height/25 ppm:
100123B
Conexant
B-3
Appendix B . Approved Crystal Vendors
BT868/Bt869
Flicker-Free Video Encoder with UltrascaleTM Technology
B-4
Conexant
100123B
0.0 Sales Offices
Further Information literature@conexant.com (800) 854-8099 (North America) (949) 483-6996 (International) Printed in USA World Headquarters Conexant Systems, Inc. 4311 Jamboree Road Newport Beach, CA 92660-3007 Phone: (949) 483-4600 Fax 1: (949) 483-4078 Fax 2: (949) 483-4391 Americas U.S. Northwest/ Pacific Northwest - Santa Clara Phone: (408) 249-9696 Fax: (408) 249-7113 U.S. Southwest - Los Angeles Phone: (805) 376-0559 Fax: (805) 376-8180 U.S. Southwest - Orange County Phone: (949) 483-9119 Fax: (949) 483-9090 U.S. Southwest - San Diego Phone: (858) 713-3374 Fax: (858) 713-4001 U.S. North Central - Illinois Phone: (630) 773-3454 Fax: (630) 773-3907 U.S. South Central - Texas Phone: (972) 733-0723 Fax: (972) 407-0639 U.S. Northeast - Massachusetts Phone: (978) 367-3200 Fax: (978) 256-6868 U.S. Southeast - North Carolina Phone: (919) 858-9110 Fax: (919) 858-8669 U.S. Southeast - Florida/ South America Phone: (727) 799-8406 Fax: (727) 799-8306 U.S. Mid-Atlantic - Pennsylvania Phone: (215) 244-6784 Fax: (215) 244-9292 Canada - Ontario Phone: (613) 271-2358 Fax: (613) 271-2359 Europe Europe Central - Germany Phone: +49 89 829-1320 Fax: +49 89 834-2734
Europe North - England Phone: +44 1344 486444 Fax: +44 1344 486555 Europe - Israel/Greece Phone: +972 9 9524000 Fax: +972 9 9573732 Europe South - France Phone: +33 1 41 44 36 51 Fax: +33 1 41 44 36 90 Europe Mediterranean - Italy Phone: +39 02 93179911 Fax: +39 02 93179913 Europe - Sweden Phone: +46 (0) 8 5091 4319 Fax: +46 (0) 8 590 041 10 Europe - Finland Phone: +358 (0) 9 85 666 435 Fax: +358 (0) 9 85 666 220 Asia - Pacific Taiwan Phone: (886-2) 2-720-0282 Fax: (886-2) 2-757-6760 Australia Phone: (61-2) 9869 4088 Fax: (61-2) 9869 4077 China - Central Phone: 86-21-6361-2515 Fax: 86-21-6361-2516 China - South Phone: (852) 2 827-0181 Fax: (852) 2 827-6488 China - South (Satellite) Phone: (86) 755-518-2495 China - North Phone: (86-10) 8529-9777 Fax: (86-10) 8529-9778 India Phone: (91-11) 692-4789 Fax: (91-11) 692-4712 Korea Phone: (82-2) 565-2880 Fax: (82-2) 565-1440 Korea (Satellite) Phone: (82-53) 745-2880 Fax: (82-53) 745-1440 Singapore Phone: (65) 737 7355 Fax: (65) 737 9077 Japan Phone: (81-3) 5371 1520 Fax: (81-3) 5371 1501
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